12.4.2
Timer Interrupt Status Register n (TMTISRn)
31
15
Bits
Mnemonic
Field Name
⎯
31:4
Reserved
Watchdog Timer
3
TWIS
Status
2
TPIBS
Pulse Generator
TMCPRB Status
1
TPIAS
Pulse Generator
TMCPRA Status
0
TIIS
Interval Timer
TMCPRA Status
0
0
Watchdog Timer TMCPRA Match Status (Initial value: 0, R/W0C)
(This bit is Reserved in the case of the TMTISR0 Register and the TMTISR1 Register.)
When in the Watchdog Timer mode, this bit is set when the counter value matches
Compare Register 2 (TMCPRA2).
This bit is cleared by writing a "0" to it.
During Read
0: Did not match the Compare Register
1: Matched the Compare Register
During Write
0: Negate interrupt
1: Invalid
Pulse Generator TMCPRB Match Status (Initial value: 0, R/W0C)
(This bit is Reserved in the case of the TMTISR2 Register.)
When in the Pulse Generator mode, this bit is set when the counter value matches
Compare Register Bn (TMCPRBn).
This bit is cleared by writing a "0" to it.
During Read
0: Did not match the Compare Register
1: Matched the Compare Register
During Write
0: Clear
1: Invalid
Pulse Generator TMCPRA Match Status (Initial value: 0, R/W0C)
(This bit is Reserved in the case of the TMTISR2 Register.)
When in the Pulse Generator mode, this bit is set when the counter value matches
Compare Register A n (TMCPRAn).
This bit is cleared by writing a "0" to it.
During Read
0: Did not match the Compare Register
1: Matched the Compare Register
During Write
0: Clear
1: Invalid
Interval Timer TMCPRA Match Status (Initial value: 0, R/W0C)
When in the Interval Timer mode, this bit is set when the counter value matches
Compare Register A n (TMCPRAn).
This bit is cleared by writing a "0" to it.
During Read
0: Did not match the Compare Register
1: Matched the Compare Register
During Write
0: Clear
1: Invalid
Figure 12.4.2 Timer Interrupt Status Register
12-11
Chapter 12 Timer/Counter
TMTISR0
0xF004
TMTISR1
0xF104
TMTISR2
0xF204
4
3
2
1
TWIS TPIBS TPIAS
R/W0C R/W0C R/W0C R/W0C : Type
0
0
0
Description
⎯
16
: Type
: Initial value
0
TIIS
0
: Initial value