Data Reception; Data Transmission - Toshiba TMPR4925 Manual

11.3.4

Data Reception

When the Serial Data Reception Disable bit (RSDE) of the Flow Control Register (SIFLCRn) is set
to "0", reception operation starts after the RXD signal start bit is detected. Start bits are detected when
the RXD signal transitions from the High state to the Low state. Therefore, the RXD signal is not
interpreted as a start bit if it is Low when the Serial Data Reception Disable bit is set to "0".
The received data are stored in the Receive FIFO. The Reception Data Full bit (RDIS) of the
DMA/Interrupt Status Register (SIDISRn) is set if the byte count of the stored reception data exceeds
the value set by the Receive FIFO Request Trigger Level field (RDIL) of the FIFO Control Register
(SIFCRn).
An interrupt is signaled when the Reception Data Interrupt Enable bit (RIE) of the DMA/Interrupt
Control Register (SIDICRn) is set. The received data can be read from the Receive FIFO Data Register
(SIRFIFOn).
In addition, DMA transfer is initiated when the Reception Data DMA Enable bit (RDE) of the
DMA/Interrupt Control Register (SIDICRn) is set.
11.3.5

Data Transmission

Data stored in the Transmission Data FIFO are transmitted when the Serial Data Transmission
Disable bit (TSDE) of the Flow Control Register (SIFLCRn) is set to "0".
If the available space in the Transmit FIFO is greater than the byte count set by the Transmit FIFO
Request Trigger Level (TDIL) of the Control Register (SIFCRn), the transmission data empty bit
(TDIS) of the DMA/Interrupt Status Register (SIDISRn) is set.
An interrupt is signaled when the Transmission Data Interrupt Enable bit (TIE) of the DMA/Interrupt
Control Register (SIDICRn) is set.
In addition, DMA transfer is initiated when the Transmission Data DMA Enable bit (TDE) of the
DMA/Interrupt Control Register (SIDICRn) is set.
Chapter 11 Serial I/O Port
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