0Xb058 (Ch. 2) 0Xb078 (Ch. 3) - Toshiba TMPR4925 Manual

8.4.2 DMA Channel Control Register (DMCCRn)
31 30 29 28
Reserved
IMMCHN
USEXFSZ
R/W R/W
0 0
15 13 12
STLTIME/INTRQD
INTENE INTENC INTENT CHNEN XFACT
R/W R/W
000 0
Bit Mnemonic Field Name
⎯
31:30 Reserved
29 IMMCHN Immediate Chain
28 USEXFSZ Transfer Set Size
Mode
27 LE Little Endian
27 26 25 24
LE
DBINH SBINH CHRST RVBYTE ACKPOL
R/W R/W R/W R/W
- 0 0 1
11 10 9 8
R/W R/W R R/W
0 0 0 0
Immediate Chain (Initial value: 0, R/W)
Selects the control method of bus ownership during chain transfer.
1: When the DMA transfer completes due to the current DMA Channel Register and
DMCCRn.CHNEN=1, DMA Command Descriptor of the address set in DMCHARn
is loaded to DMA channel Register without bus ownership release. (Chain
Transfer)
0: When the DMA transfer completes due to the current DMA Channel Register and
DMCCRn.CHNEN=1, DMA controller once releases the bus ownership. After that
it gets bus ownership again and starts Chain Transfer.
Note: It is not concerned with the setup of this bit but DMA controller releases bus
ownership after the Chain Transfer ends.
Use Transfer Set Size (Initial value: 0, R/W)
Selects the DMA channel operation mode during Burst DMA transfer. Refer to
"8.3.7.2 Burst Transfer During Single Address Transfer" and "8.3.8.2 Burst Transfer
During Dual Address Transfer" for more information.
1: The DMA Controller always transfers the amount of data set in DMCCRn.XFSZ for
each bus operation. Since alignment to the boundary of the DMCCRn.XFSZ in the
address is not forced when in this mode, transfers that exceed 32 -word
boundaries are divided into two operations.
0: The DMA Controller calculates the transfer size so the address set in DMSARn
and DMDARn (only during Dual Address transfer) can be aligned to the boundary
of the size set in DMCCRn.XFSZ, then transfers data according to that size.
Note: During dual address transfer, "0" becomes effective only when MSARn and
DMDARn are aligned on a word boundary, and the value of DMCNTRn is a
multiple of 4-byte.
Little Endian (Initial value: value that is the opposite of the G-Bus Endian
(CCFG.ENDIAN), R/W)
This bit sets the Endian of the channel. Use the initial value.
1: Channel operates in the Little Endian mode
0: Channel operates in the Big Endian mode
Figure 8.4.2 DMA Channel Control Register (1/4)
8-24
Chapter 8 DMA Controller
0xB018 (ch. 0)
0xB058 (ch. 2)
23 22 21 20 19
REQPL EGREQ CHDN
R/W R/W R/W R/W R/W
0 0 0 0
7 6 5 4
Reserved XFSZ
SMPCHN
R/W R/W R/W
00 0 000
Description
⎯
0xB038 (ch. 1)
0xB078 (ch. 3)
18 17 16
DNCTL
EXTRQ
R/W R/W : Type
0 00 0 : Initial value
2 1 0
MEMIO SNGAD
R/W R/W : Type
0 0 : Initial value