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11.3.6
DMA Transfer
The DMA Request Control Register (DRQCTR)of the DMA Request Select field (DMAREQ[3:0])
can be used to allocate DMA channels for each reception and transmission channel in the following
manner.
SIO Channel 1 Reception
SIO Channel 1 Transmission
SIO Channel 0 Reception
SIO Channel 0 Transmission
Set the DMA Channel Control Register of the DMA Controller as described below.
DMA Request Polarity
DMA Acknowledge Polarity
Request Detection
Transfer Size
Transfer Address Mode
In the case of transmission channels, the address of the Transmit FIFO Register (SITFIFOn) is set in
the DMAC Destination Address Register (DMDARn). In the case of reception channels, the address of
the Receive FIFO Register (SIRFIFOn) is set in the DMAC Source Address Register (DMSARn).
Please set the addresses specified in "11.4.8 Transmit FIFO Register" and "11.4.9 Receive FIFO
Register" since the set address differs depending on the Endian mode.
11.3.7
Flow Control
SIO supports hardware flow control that uses the RTS*/CTS* signal.
The CTS* (Clear to Send) input signal indicates that data can be received from the reception side
when it is Low. Setting the Transmission Enable Select bit (TES) of the Flow Control Register
(SIFLCRn) makes transmission flow control that uses the CTS* signal more effective.
It is also possible to generate status change interrupts by changing the state of the CTS* signal. The
conditions in which interrupts are generated can be selected by the CTSS Active Condition field of the
DMA/Interrupt Control Register (SIDICRn).
Setting the RTS* (Request to Send) output signal to High requests the transmission side to pause
transmission. Transmission resumes when the reception side becomes ready and the RTS* signal is set
to Low.
Setting the Reception Enable Select bit (RCS) of the flow Control Register (SIFLCRn) makes
reception flow control that uses the RTS* signal more effective. The RTS* signal pin status becomes
High when data of the byte count set by the RTS Active Trigger Level field (RTSTL) of the Flow
Control Register (SIFLCRn) accumulates in the Receive FIFO. The RTS* signal can also be made High
by setting the RTS Software Control bit (RTSSC) of the Flow Control Register (SIFLCRn). Setting this
bit requests the transmission side to pause transmission.
Chapter 11 Serial I/O Port
DMA Channel 0
DMA Channel 1
DMA Channel 2
DMA Channel 3
Low Active
DMCCRn.ACKPOL = 0
Low Active
DMCCRn.REQPOL = 0
Level Detection
DMCCRn.EGREQ = 0
1 Byte
DMCCRn.XFSZ = 000b
Dual
DMCCRn.SNGAD = 0
11-8
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