Toshiba TMPR4925 Manual page 72

Table 3.2.2 Boot Configuration Specified with the ADDR[19:0], TDO, UAE and SADDR10 Signals (2/2)
Signal
ADDR[8:6] Select Boot Memory
Selects boot memory.
HHH = Device connected to channel 0 of the external bus controller
(clock frequency division ratio: 1/1)
HHL = Device connected to channel 0 of the external bus controller
(clock frequency division ratio: 1/2)
HLH = Device connected to channel 0 of the external bus controller
(clock frequency division ratio: 1/3)
HLL = Reserved
LHH = PCI boot
LHL = Reserved
LLH = Reserved
LLL = Reserved
ADDR[5] Boot ACK* Input
Specifies the access mode for external bus controller channel 0.
L = ACK* Input Mode Enable
H = ACK* Input Mode Disable
ADDR[4:3] Select SYSCLK Frequency
Specifies the division ratio of the SYSCLK frequency to the G-Bus clock
(GBUSCLK) frequency.
LL = 4 (SYSCLK frequency = GBUSCLK frequency/4)
LH = 3 (SYSCLK frequency = GBUSCLK frequency/3)
HL = 2 (SYSCLK frequency = GBUSCLK frequency/2)
HH = 1 (SYSCLK frequency = GBUSCLK frequency)
ADDR[2] Reserved
This signal will not be set to 0 upon booting.
ADDR[1] PCI Arbiter Select
Selects a PCI bus arbiter.
L = External PCI bus arbiter.
H = Built-in PCI bus arbiter.
ADDR[0] TX49/H2 Internal Timer Interrupt Disable
Specifies whether timer interrupts within the TX49/H2 core are enabled.
L = Enable timer interrupts within the TX49/H2 core.
H = Disable timer interrupts within the TX49/H2 core.
TDO PC Trace
Specifies whether PIO[31:20] and BC32K are used as PC trace signals.
L = Use as TPC[3:1], PCST[7:0] and DCLK
H = Use as PIO[31:20] and BC32K
UAE Reserved
Used for testing. Because this signal is used for setting a clock
frequency, ensure that the signal will not be set to 0 upon booting.
SADDR10 Reserved
Used for testing. Because this signal is used for setting a clock
frequency, ensure that the signal will not be set to 0 upon booting.
Description
3-14
Chapter 3 Signals
Corresponding Configuration
Register Bit Determined at
EBCCR0.ME RESET* deassert
edge
RESET* deassert
EBCCR0.EACK
edge
CCFG. SYSSP PON* deassert edge
⎯
RESET*deassert
edge
CCFG.PCIARB RESET* deassert
edge
CCFG.TINTDIS RESET* deassert
edge
CCFG.PCTRCE PON* deassert edge
CCFG.bit[28] PON* deassert edge
⎯
PON* deassert edge