Chapter 9 SDRAM Controller
9.5.6
Single Read (16-bit Bus)
SDCLK
SDCS*
ADDR [19:16]
SADDR10
7fff
0000
ADDR[14:5]
RAS*
CAS*
WE*
CKE
f
f
0
DQM [3:0]
DATA [15:0]
ACK*/READY*
= 2, t
= 2, t
= 0, 16-bit Bus)
Figure 9.5.8 One Word Single Read (t
RCD
CASL
DA
9-25