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11.3.8
Reception Data Status
Status data such as the following is also stored in the Receive FIFO.
•
Overrun error
An overrun error is generated if all 16-stage Receive FIFO buffers become full and more data is
transferred to the Reception Read buffer. When this occurs, the Overrun Status bit is set by the last
stage of the Receive FIFO.
•
Parity error
A parity error is generated when a parity error is detected in the reception data.
•
Framing error
A framing error is generated when "0" is detected at the first stop bit of the reception data.
•
Break reception
A break is detected when a framing error occurs in the reception data and all data in a single
frame are "0". When this occurs, 2 frames (2 Bytes) of 0x00 data are stored in the Receive FIFO.
The Reception Error Interrupt bit (SIDISR.ERI) of the DMA/Interrupt Status Register (SIDISRn) is
set when one of the following errors is detected: an overrun error, a parity error, or a framing error. An
interrupt is signaled if the Reception Error Interrupt Enable bit of the DMA/Interrupt Control Register
(SIDICRn) is set.
The Receive Break bit (RBRKD) and the Receiving Break bit (RBRKD) of the Status Change
Interrupt Status Register (SISCISR) is set when a break is detected. The Receive Break bit (RBRKD)
remains set until it is cleared by the software. The Receiving Break bit (RBRKD) is automatically
cleared when a frame is received that is not a break.
The status of the next reception data to be read is set to the Overrun Error bit (UOER), Parity Error
bit (UPER), Framing Error bit (UFER), and the Receive Break bit (RBRKD). Each of these statuses is
updated when reception data is read from the Receive FIFO Register (SIRFIFOn).
During DMA transfer, an error is signaled and DMA transfer stops with error data remaining in the
Receive FIFO if either an error (Framing Error, Parity Error, or Overrun Error) or a Reception time out
(TOUT) is detected. If a Reception Error occurs during DMA transfer, use the Receive FIFO Reset bit
(RFRST) of the FIFO Control Register (SIFCRn) to clear the Receive FIFO. However, a software reset
will be required if a reception overrun error has occurred. Refer to "11.3.10 Software Reset" for more
information.
Chapter 11 Serial I/O Port
11-9
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