P2G Memory Space 2 Control Register (P2Gm2Ctr) 0Xd194 - Toshiba TMPR4925 Manual

10.4.50 P2G Memory Space 2 Control Register (P2GM2CTR)
31 29 28
Reserved
15
Reserved
Bits Mnemonic Field Name
⎯
31:29 Reserved
28:20 AM[28:20] Address Mask
⎯
19:11 Reserved
10:8 TPRBL Target Prefetch
Read Burst
Length
⎯
7:5 Reserved
4 TMCC Target Memory
space 2 Cache
Clear
⎯
3 Reserved
2 MEM2PE Memory 2
Window Space
Prefetch Enable
1 P2GM1EN Memory Space 2
Enable
0 BSWAP Byte Swap
Figure 10.4.50 P2G Memory Space 2 Control Register
AM[28:20]
R/W
0x000
11 10 8
TPRBL
R/W
010
PCI-Bus to G-Bus Address Mask (Initial value: 0x000, R)
Sets the bits to be subject to address comparison. See 10.3.4 for more information.
When setting a memory space size of 256 MB (0x1000_0000) for example, the value
becomes 0x0FF.
Target Prefetch Read Burst Length (Initial value: 0x3, R/W)
These bits set the G-Bus Burst Size (in DWORDS, (32-bit words)) to be read into the
data FIFO during a target memory Read operation.
0x000: Access and transfer 1DWORD (NO BURST)
0x001: Access and transfer 4 DWORDs of data to the target read FIFO.
0x010: Access and transfer 8 DWORDs of data to the target read FIFO.
0x011: Access and transfer 16 DWORDs of data to the target read FIFO.
0x1xx: Access and transfer 32 DWORDs of data to the target read FIFO.
Target Memory space 1 Cache Clear (Initial value: 0, R/W)
A write of 1 will flush the Target Memory Cache 2. This bit is cleared automatically.
1: Cache Clear
0: Don't care
Note: This bit is always set to "0". (Initial value: 0, R/W)
Memory 2 Window Prefetch Enable (Initial value: 0, R/W)
If this bit is set, Prefetching of G-Bus data will occur on Target Memory Reads. If this
bit is cleared, 1 Burst of length TPRBL will be done on the G-Bus.
Even if the setting of this bit is changed, prefetchable bits in the Base Address
Register of the PCI Configuration Space will not reflect this change. We recommend
using the default setting when the PCI Controller is in the Satellite mode.
Target Memory Space 2 Enable (Initial value: 0, R/W) Controls whether Memory
Space 2 for target access is valid or invalid.
When this bit is set to invalid, Writes to the Memory Space 2 Lower Base Address
Register or the Memory Space 2 Upper Base Address Register of the PCI
Configuration Register become invalid. Also, "0" is returned to Reads as a response.
1: Validates Memory Space 2 for target access.
0: Invalidates Memory Space 2 for target access.
Byte Swap Disable
(Initial value: Little Endian Mode: 0; Big Endian Mode: 1, R/W) Sets the byte swapping
of Memory Space 2 for target access.
0: Do not perform byte swapping.
1: Perform byte swapping.
Please use the default state in most situations. If this bit is changed to "0" when in the
Big Endian Mode, the byte order of transfer to Memory Space 2 through DWORD (32-
bit) access will not change.
10-79
Chapter 10 PCI Controller
20 19
7 5 4
Reserved TMCC
Reserved MEM1PE
R/W R/W
0
Description
⎯
⎯
⎯
0xD194
16
Reserved
: Type
: Initial value
3 2 1 0
BSWAP
P2GM1EN
R/W R/W R/W : Type
0 0 0 0/1 : Initial value