Toshiba TMPR4925 Manual page 124

Chapter 7 External Bus Controller
SYSCLK
CE*
ADDR [19:0]
OE*
DATA [31:0]
ACK*/READY (Input)
Latch Data
Acknowledge ACK*
EBCCRn.SHWT=0
EBCCRn.LDEA=1
Figure 7.3.10 ACK* Input Timing (Single Read Cycle)
SYSCLK
CE*
ADDR [19:0]
3 clocks
SWE*/BWE*
DATA [31:0]
4 clocks
ACK*/READY (Input)
Acknowledge ACK*
EBCCRn.SHWT=0
Figure 7.3.11 ACK* Input Timing (Single Write Cycle)
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