Toshiba TMPR4925 Manual

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64-Bit TX System RISC

TX49 Family

TMPR4925

Rev. 3.0

Table of Contents

Summary of Contents for Toshiba TMPR4925

Page 1 64-Bit TX System RISC TX49 Family TMPR4925 Rev. 3.0...
Page 2 Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
Page 3 TMPR4925 64-bit RISC microprocessor. This databook is written so as to be accessible to engineers who may be designing a TOSHIBA microprocessor into their products for the first time. No prior knowledge of this device is assumed. What we offer here is basic information about the microprocessor, a discussion of the application fields in which the microprocessor is utilized, and an overview of design methods.
Page 5: Table Of Contents
Table of Contents Table of Contents Handling Precautions TX4925 1. Features................................... 1-1 Outline ................................1-1 Features ................................1-2 1.2.1 TX49/H2 Processor Core Features......................1-2 1.2.2 TX4925 Peripheral Circuit Features...................... 1-3 2. Block Diagram................................ 2-1 TX4925 Block Diagram..........................2-1 3. Signals ..................................3-1 Pin Signal Description ...........................
Page 6 Table of Contents 5.2.11 Register Address Mapping Register (RAMP) 0xE030............... 5-14 6. Clocks ..................................6-1 TX4925 Clock Signals ........................... 6-1 Power-Down Mode ............................6-5 6.2.1 Halt Mode and Doze Mode ........................6-5 6.2.2 Power Reduction for Peripheral Modules ..................... 6-5 6.2.3 Power-Down Mode ..........................
Page 7 Table of Contents 8.3.15 Restrictions in Access to PCI Bus ....................... 8-20 Registers............................... 8-21 8.4.1 DMA Master Control Register (DMMCR) 0xB0A8 ................8-22 8.4.2 DMA Channel Control Register (DMCCRn) 0xB018 (ch. 0) 0xB038 (ch. 1) 0xB058 (ch. 2) 0xB078 (ch. 3)......................8-24 8.4.3 DMA Channel Status Register (DMCSRn) 0xB01C (ch.
Page 8 Table of Contents 9.5.2 Single Write (32-bit Bus) ........................9-20 9.5.3 Burst Read (32-bit Bus)........................9-22 9.5.4 Burst Write (32-bit Bus) ........................9-23 9.5.5 Burst Write (32-bit Bus, Slow Write Burst) ..................9-24 9.5.6 Single Read (16-bit Bus) ........................9-25 9.5.7 Single Write (16-bit Bus) ........................
Page 9 Table of Contents 10.4.27 PCI Bus Arbiter Current Request Register (PBACREQ) 0xD114 ............ 10-56 10.4.28 PCI Bus Arbiter Current Grant Register (PBACGNT) 0xD118 ............10-57 10.4.29 PCI Bus Arbiter Current State Register (PBACSTATE) 0xD11C ............. 10-58 10.4.30 G2P Memory Space 0 G-Bus Base Address Register (G2PM0GBASE) 0xD120......10-59 10.4.31 G2P Memory Space 1 G-Bus Base Address Register (G2PM1GBASE) 0xD128......
Page 10 Table of Contents 11.3.11 Error Detection/Interrupt Signaling....................11-11 11.3.12 Multi-Controller System ........................11-12 11.4 Registers..............................11-13 11.4.1 Line Control Register 0 (SILCR0) 0xF300 (Ch. 0) Line Control Register 1 (SILCR1) 0xF400 (Ch. 1) ...........................11-14 11.4.2 DMA/Interrupt Control Register 0 (SIDICR0) 0xF304 (Ch. 0) DMA/Interrupt Control Register 1 (SIDICR1) 0xF404 (Ch.
Page 11 Table of Contents 14.1 Features ................................ 14-1 14.2 Configuration ............................... 14-2 14.3 Functional Description..........................14-3 14.3.1 CODEC Connection ..........................14-3 14.3.2 Pin Configuration ..........................14-4 14.3.3 Usage Flow............................14-5 14.3.4 AC-link Start Up ..........................14-7 14.3.5 CODEC Register Access ........................14-8 14.3.6 Sample-data Transmission and Reception...................
Page 12 Table of Contents 15.4.12 Interrupt Mask Level Register (IRMSK) 0xF640 ................15-22 15.4.13 Interrupt Edge Detection Clear Register (IREDC) 0xF660............... 15-23 15.4.14 Interrupt Pending Register (IRPND) 0xF680..................15-24 15.4.15 Interrupt Current Status Register (IRCS) 0xF6A0 ................15-27 15.4.16 Interrupt Request Flag Register 0 (IRFLAG0) 0xF510..............15-29 15.4.17 Interrupt Request Flag Register 1 (IRFLAG1) 0xF514..............
Page 13 Table of Contents 18.1 Characteristics.............................. 18-1 18.2 Block Diagram ............................. 18-1 18.3 Detailed Explanation............................ 18-2 18.3.1 Access to NAND Flash Memory......................18-2 18.3.2 ECC Control............................18-4 18.4 Registers............................... 18-5 18.4.1 NAND Flash Memory Data Transfer Register (NDFDTR) 0xC000 ........... 18-5 18.4.2 NAND Flash Memory Mode Control Register (NDFMCR) 0xC004 ..........
Page 14 Table of Contents 22.5.6 DMA Interface AC Characteristics...................... 22-8 22.5.7 Interrupt Interface AC Characteristics....................22-10 22.5.8 SIO Interface AC Characteristics ...................... 22-10 22.5.9 Timer Interface AC Characteristics ....................22-11 22.5.10 PIO Interface AC Characteristics .......................22-11 22.5.11 AC-link Interface AC Characteristics....................22-12 22.5.12 NAND Flash Memory Interface AC Characteristics .................
Page 15 Handling Precautions...
Page 17 It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property.
Page 18 1 Using Toshiba Semiconductors Safely...
Page 19: Safety Precautions
2 Safety Precautions 2. Safety Precautions This section lists important precautions which users of semiconductor devices (and anyone else) should observe in order to avoid injury and damage to property, and to ensure safe and correct use of devices. Please be sure that you understand the meanings of the labels and the graphic symbol described below before you move on to the detailed descriptions of the precautions.
Page 20 2 Safety Precautions General Precautions regarding Semiconductor Devices Do not use devices under conditions exceeding their absolute maximum ratings (e.g. current, voltage, power dissipation or temperature). This may cause the device to break down, degrade its performance, or cause it to catch fire or explode resulting in injury. Do not insert devices in the wrong orientation.
Page 21 2 Safety Precautions Precautions Specific to Each Product Group 2.2.1 Optical semiconductor devices When a visible semiconductor laser is operating, do not look directly into the laser beam or look through the optical system. This is highly likely to impair vision, and in the worst case may cause blindness. If it is necessary to examine the laser apparatus, for example to inspect its optical characteristics, always wear the appropriate type of laser protective glasses as stipulated by IEC standard IEC825-1.
Page 22 2 Safety Precautions Do not use devices under conditions which exceed their absolute maximum ratings (current, voltage, power dissipation, temperature etc.). This may cause the device to break down, causing a large short-circuit current to flow, which may in turn cause it to catch fire or explode, resulting in fire or injury.
Page 23 3 General Safety Precautions and Usage Considerations 3. General Safety Precautions and Usage Considerations This section is designed to help you gain a better understanding of semiconductor devices, so as to ensure the safety, quality and reliability of the devices which you incorporate into your designs. From Incoming to Shipping 3.1.1 Electrostatic discharge (ESD)
Page 24 3 General Safety Precautions and Usage Considerations (e) Make sure that sections of the tape carrier which come into contact with installation devices or other electrical machinery are made of a low-resistance material. (f) Make sure that jigs and tools used in the assembly process do not touch devices. (g) In processes in which packages may retain an electrostatic charge, use an ionizer to neutralize the ions.
Page 25 3 General Safety Precautions and Usage Considerations • When storing printed circuit boards which have devices mounted on them, use a board container or bag that is protected against static charge. To avoid the occurrence of static charge or discharge due to friction, keep the boards separate from one other and do not stack them directly on top of one another.
Page 26 3 General Safety Precautions and Usage Considerations Storage 3.2.1 General storage • Avoid storage locations where devices will be exposed to moisture or direct sunlight. • Follow the instructions printed on the device cartons regarding transportation and storage. Temperature: • Humidity: The storage area temperature should be kept within a temperature range of 5°C to 35°C, and relative humidity should be maintained at between...
Page 27 3 General Safety Precautions and Usage Considerations • If the 12-month storage period has expired, or if the 30% humidity indicator shown in Figure 1 is pink when the packing is opened, it may be advisable, depending on the device and packing type, to back the devices at high temperature to remove any moisture.
Page 28: Absolute Maximum Ratings
This section describes some general precautions which you should observe when designing circuits and when mounting devices on printed circuit boards. For more detailed information about each product family, refer to the relevant individual technical datasheets available from Toshiba. 3.3.1 Absolute maximum ratings Do not use devices under conditions in which their absolute maximum ratings (e.g.
Page 29 3 General Safety Precautions and Usage Considerations CMOS logic IC inputs, for example, have extremely high impedance. If an input pin is left open, it can easily pick up extraneous noise and become unstable. In this case, if the input voltage level reaches an intermediate level, it is possible that both the P-channel and N-channel transistors will be turned on, allowing unwanted supply current to flow.
Page 30 For details of how to interface particular devices, consult the relevant technical datasheets and databooks. If you have any questions or doubts about interfacing, contact your nearest Toshiba office or distributor.
Page 31 3 General Safety Precautions and Usage Considerations 3.3.10 Decoupling Spike currents generated during switching can cause Vcc (Vdd) and GND (Vss) voltage levels to fluctuate, causing ringing in the output waveform or a delay in response speed. (The power supply and GND wiring impedance is normally 50 Ω...
Page 32: Safety Standards
3 General Safety Precautions and Usage Considerations 3.3.13 Peripheral circuits In most cases semiconductor devices are used with peripheral circuits and components. The input and output signal voltages and currents in these circuits must be chosen to match the semiconductor device’s specifications. The following factors must be taken into account.
Page 33 3 General Safety Precautions and Usage Considerations 3.4.2 Inspection Sequence Do not insert devices in the wrong orientation. Make sure that the positive and negative electrodes of the power supply are correctly connected. Otherwise, the rated maximum current or maximum power dissipation may be exceeded and the device may break down or undergo performance degradation, causing it to catch fire or explode, resulting in injury to the user.
Page 34 3 General Safety Precautions and Usage Considerations (1) Lead insertion hole intervals on the printed circuit board should match the lead pitch of the device precisely. (2) If lead insertion hole intervals on the printed circuit board do not precisely match the lead pitch of the device, do not attempt to forcibly insert devices by pressing on them or by pulling on their leads.
Page 35 3 General Safety Precautions and Usage Considerations (2) Using medium infrared ray reflow • Heating top and bottom with long or medium infrared rays is recommended (see Figure 3). Medium infrared ray heater (reflow) Product flow Long infrared ray heater (preheating) Figure 3 Heating top and bottom with long or medium infrared rays •...
Page 36 Electrical contact may also cause a chip to fail. Therefore, when mounting devices, make sure that nothing comes into electrical contact with the reverse side of the chip. If your design requires connecting the reverse side of the chip to the circuit board, please consult Toshiba or a Toshiba distributor beforehand.
Page 37 (2) When handling chips, be careful not to expose them to static electricity. In particular, measures must be taken to prevent static damage during the mounting of chips. With this in mind, Toshiba recommend mounting all peripheral parts first and then mounting chips last (after all other components have been mounted).
Page 38 3 General Safety Precautions and Usage Considerations 3.5.10 Tightening torque (1) Make sure the screws are tightened with fastening torques not exceeding the torque values stipulated in individual datasheets and databooks for the devices used. (2) Do not allow a power screwdriver (electrical or air-driven) to touch devices. 3.5.11 Repeated device mounting and usage Do not remount or re-use devices which fall into the categories listed below;...
Page 39 3 General Safety Precautions and Usage Considerations 3.6.5 Strong electrical and magnetic fields Devices exposed to strong magnetic fields can undergo a polarization phenomenon in their plastic material, or within the chip, which gives rise to abnormal symptoms such as impedance changes or increased leakage current.
Page 40 3 General Safety Precautions and Usage Considerations 3-18...
Page 41 Resonators recommended for use with Toshiba products in microcontroller oscillator applications are listed in Toshiba databooks along with information about oscillation conditions. If you use a resonator not included in this list, please consult Toshiba or the resonator manufacturer concerning the suitability of the device for your application.
Page 42 4 Precautions and Usage Considerations...
Page 43 TMPR4925...
Page 45 Conventions in this Manual Conventions in this Manual Value Conventions • Hexadecimal values are expressed as in the following example. (This value is expressed as 42 in the decimal system.) • KB (kilobyte) = 1,024 Bytes, MB (megabyte) = 1,024 × 1,024 = 1,048,576 Bytes, GB (gigabyte) = 1,024 ×...
Page 46 Any function described as a “diagnostic function” is used to facilitate operation evaluations. The operation of such functions is not guaranteed. References 64-bit TX System RISC TX49/H2 Core Architecture User’s Manual (http://www.semicon.toshiba.co.jp/eng/index.html) MIPS RISC Architecture, Gerry Kane and Joe Heinrich (ISBN 0-13-590472-2) See MIPS Run, Dominic Sweetman (ISBN 1-55860-410-3) MIPS Publications (http://www.mips.com/publications/) PCI Local Bus Specification Revision 2.2 (http://www.pcisig.com/)
Page 47: Features
The TMPR4925XB, to be referred as TX4925 MIPS RISC micro-controller is a highly integrated ASSP solution based on Toshiba’s TX49/H2 processor core, a 64-bit MIPS I, II, III ISA Instruction Set Architecture (ISA) compatible with additional instructions. For information on the architecture of the TX49/H2 core, including the instruction set, refer to the manual 64-bit TX System RISC, TX49/H2 Core Architecture.
Page 48: Tx49/H2 Processor Core Features
• IEEE1149.1 (JTAG) support: Debug Support Unit (Enhanced JTAG) • 256-pin PBGA package 1.2.1 TX49/H2 Processor Core Features The TX49/H2 is a high-performance 64-bit microprocessor core developed by Toshiba. • 64-bit operation • 32-, 64-bit integer general purpose registers •...
Page 49: Tx4925 Peripheral Circuit Features
Chapter 1 Features 1.2.2 TX4925 Peripheral Circuit Features 1.2.2.1 External Bus Controller (EBUSC) The External Bus Controller generates necessary signals to control external memory and I/O devices. • 6 channels of chip select signals, enabling control of up to six devices •...
Page 50 Chapter 1 Features 1.2.2.3 SDRAM Controller (SDRAMC) The SDRAM Controller generates necessary control signals for the SDRAM interface. It has four channels and can handle up to 2G bytes (512 MB/channel) of memory by supporting a variety of memory configurations. •...
Page 51 Chapter 1 Features 1.2.2.6 Timers/Counters Controller (TMR) The TX4925 contains 3-channel timer/counters. • 3-channel 32-bit up-counter • Supports three modes : interval timer mode, pulse generator mode, and watchdog timer mode • 2 timer output pins • 1 count clock input pin 1.2.2.7 Parallel I/O Ports (PIO) The TX4925 contains 32-bit parallel I/O ports...
Page 52 Chapter 1 Features 1.2.2.10 high-speed serial Concentration Highway Interface (CHI) The TX4925 has a CHI module. • Contents logic for interfacing to external full-duplex serial time-division-multiplexed (TDM) communication peripherals • Supports ISDN line interface chips and other PCM/TDM serial devices •...
Page 53 Chapter 1 Features 1.2.2.16 EJTAG Interface The TX4925 contains an Extended Enhanced Joint Test Action Group (Extended EJTAG) interface, which provides two functions: JTAG boundary scan test that complies with IEEE1149.1 and real-time debugging using a debug support unit (DSU) built into the TX49/H2 core. •...
Page 54 Chapter 1 Features...
Page 55: Block Diagram
Chapter 2 Block Diagram Block Diagram TX4925 Block Diagram TX49/H2 Core RESET I-Cache TDI / DINT* TDO / TPC[0] CPU core TPC[3:1] D-Cache TRST* DCLK PCST[8:0] G-Bus I/F TEST* SDCLK[1:0] TEST SCAN_ENB* SDCLKIN MASTERCLK SDCS[3:0]* SADDR10 PCICLK[2:1] SDRAMC PCICLK_IO (4ch.) RAS* PCIAD [31:0] CAS*...
Page 56 Chapter 2 Block Diagram Figure 2.1.1 shows a diagram of the TX4925. The each block is itemized below. (1) TX49/H2 core • It is composed of CPU, System Control Coprocessor (CP0), Instruction Cache, Data Cache, Floating-Point Unit (FPU), Write Buffer (WBU), Debug Support Unit (DSU) and G-Bus I/F. −...
Page 57 Chapter 2 Block Diagram (13) NDFMC • NAND Flash memory Controller, Supports ECC (Error Correction Code) function (14) RTC • Real Time Clock, 44-bit up-counter (15) EBIF • External Bus Interface, Connects between 20-bit external address bus/32-bit external data bus and SDRAMC/EBUSC (16) CG •...
Page 58 Chapter 2 Block Diagram...
Page 59: Signals
Chapter 3 Signals Signals Pin Signal Description In the following tables, asterisks at the end of signal names indicate active-low signals. In the Type column, PU indicates that the pin is equipped with an internal pull-up resister and PD indicates that the pin is equipped with an internal pull-down resister.
Page 60: Sdram Interface Signals
Chapter 3 Signals 3.1.2 SDRAM Interface Signals Table 3.1.2 SDRAM Interface Signals Signal Name Type Description Initial State SDCLK[1:0] Output SDRAM Controller Clock All High Clock signals used by SDRAM/SyncFlash. The clock frequency is the same as the G- Bus clock (GBUSCLK) frequency. When these clock signals are not used, the pins can be set to L using the SDCLK Enable field of the pin configuration register (PCFG.SDCLKEN[1:0]).
Page 61: External Interface Signals
Chapter 3 Signals 3.1.3 External Interface Signals Table 3.1.3 External Interface Signals (1/2) Signal Name Type Description Initial State SYSCLK Output System Clock High Clock for external I/O devices. Outputs a clock in full speed mode (at the same frequency as the G-Bus clock (GBUSCLK) frequency), half speed mode (at one half the GBUSCLK frequency), third speed mode (at one third the GBUSCLK frequency), or quarter speed mode (at one quarter the GBUSCLK frequency).
Page 62 Chapter 3 Signals Table 3.1.3 External Interface Signals (2/2) Signal Name Type Description Initial State CARD1CSH* Output PCMCIA card slot 1 chip select PIO input CARD1CSL* Chip select signals for PCMCIA card slot 1. The pins are shared with other functions (refer to Section "3.3 Pin Multiplexing"). CARD2CSH* Output PCMCIA card slot 2 chip select...
Page 63: Dma Interface Signals
Chapter 3 Signals 3.1.4 DMA Interface Signals Table 3.1.4 DMA Interface Signals Signal Name Type Description Initial State DMAREQ[1:0] Input DMA Request PIO input DMA transfer request signals from an external I/O device. The pins are shared with other functions (refer to Section "3.3 Pin Multiplexing"). DMAACK[1:0] Output DMA Acknowledge...
Page 64 Chapter 3 Signals Table 3.1.5 PCI Interface Signals (2/2) Signal Name Type Description Initial State REQ[3:2]* Input Request Input Signals used by the master to request bus mastership. The boot configuration signal on the ADDR[1] pin determines whether the built-in PCI bus arbiter is used.
Page 65: Serial I/O Interface Signals
Chapter 3 Signals 3.1.6 Serial I/O Interface Signals Table 3.1.6 Serial I/O Interface Signals Signal Name Type Description Initial State CTS [1:0]* Input SIO Clear to Send PIO input PU *1 CTS* signals. The pins are shared with other functions (refer to Section "3.3 Pin Multiplexing"). RTS [1:0]* Output SIO Request to Send...
Page 66: Ac-Link Interface Signals
Chapter 3 Signals 3.1.9 AC-link Interface Signals Table 3.1.9 AC-link Interface Signals Signal Name Type Description Initial State ACRESET* Output AC '97 Master H/W Reset PIO input The pin is shared with other functions (refer to Section "3.3 Pin Multiplexing"). SYNC Output 48 kHz Fixed Rate Sample Sync...
Page 67: Spi Interface Signals
Chapter 3 Signals 3.1.12 SPI Interface Signals Table 3.1.12 SPI Interface Signals Signal Name Type Description Initial State SPICLK Output SPI Clock PIO input This pin is used for a data clock to or from an SPI slave device. The pin is shared with other functions (refer to Section "3.3 Pin Multiplexing"). SPIOUT Output SPI Data Output...
Page 68: Clock Signals
Chapter 3 Signals Table 3.1.14 Extended EJTAG Interface Signals (2/2) Signal Name Type Description Initial State TPC[3:1] Output PC Trace Output Selected by TPC[3:1] output the value of the noncontiguous program counter in sync with DCLK. H: PIO input The pins are shared with other functions (refer to Section "3.3 Pin Multiplexing"). L: All High Input JTAG Test Mode Select Input...
Page 69: Test Signals
Chapter 3 Signals 3.1.17 Test Signals Table 3.1.17 Test Signals Signal Name Type Description Initial State TEST* Input Test Mode Setting Input Test pin. This pin must be fixed to High. SCANENB* Input Scan Mode Test Control Input Test pin. This pin must be fixed to High. 3.1.18 Power Supply Pins Table 3.1.18 Power Supply Pins...
Page 70: Boot Configuration
Chapter 3 Signals Boot Configuration The ADDR[19:0], UAE, SADDR10 and TDO signals can also function as configuration signals for initially setting various functions upon booting the system. The states of the configuration signals immediately after the RESET* or PON* signal is deasserted are read as initial values for the TX4925 internal registers.
Page 71 Chapter 3 Signals Table 3.2.2 Boot Configuration Specified with the ADDR[19:0], TDO, UAE and SADDR10 Signals (1/2) Corresponding Configuration Signal Description Register Bit Determined at ADDR[19] Reserved CCFG bit [12] RESET* deassert edge This signal will be set to 0 upon booting. ADDR[18] PCI Clock Enable PCFG.
Page 72 Chapter 3 Signals Table 3.2.2 Boot Configuration Specified with the ADDR[19:0], TDO, UAE and SADDR10 Signals (2/2) Corresponding Configuration Signal Description Register Bit Determined at ADDR[8:6] Select Boot Memory EBCCR0.ME RESET* deassert edge Selects boot memory. HHH = Device connected to channel 0 of the external bus controller (clock frequency division ratio: 1/1) HHL = Device connected to channel 0 of the external bus controller (clock frequency division ratio: 1/2)
Page 73: Pin Multiplexing
Chapter 3 Signals Pin Multiplexing The TX4925 has 35 multiplexed pins as shown in Table 3.3.1. Each pin is used for different functions depending on the settings of the PCFG control register or the TDO boot configuration signal. Table 3.3.2 to Table 3.3.8 show how to set the function for each pin.
Page 74 Chapter 3 Signals Table 3.3.2 Function Selection for PIO[31:24] (1) PCFG Control Bits Boot Signal Pin Name Function SELCARD[1] SELCARD[0] SELCE[1] SELCE[0] SELCHI TPC[2] PIO[31] CARDDIR* PIO[31] PCST[8] PIO[30] CARDREG* PIO[30] PCST[6] CARD2CSH* PIO[29] CE[5]* PIO[29] PCST[7] CARD2CSL* PIO[28] CE[4]* PIO[28] PCST[5] CHIDOUT...
Page 75 Chapter 3 Signals Table 3.3.4 Function Selection for PIO[20:18] (3) PCFG Control Bits Boot Signal Pin Name Function SELCHI SELTMR[1] SELTMR[0] PCST[1] PIO[20] PIO[20] TIMER[0] CHIFS PIO[19] PIO[19] TIMER[1] CHICLK PIO[18] PIO[18] CHIDIN Table 3.3.5 Function Selection for PIO[17:12] (4) PCFG Control Bits Boot Signal Pin Name...
Page 76 Chapter 3 Signals Table 3.3.6 Function Selection for PIO[11:8] (5) PCFG Control Bits Boot Signal Pin Name Function SELSIO[0] SELSIOC[0] PIO[11] PIO[11] TXD[0] PIO[10] PIO[10] RXD[0] PIO[9] PIO[9] RTS[0] PIO[8] PIO[8] CTS[0] Table 3.3.7 Function Selection for PIO[7:5] (6) Boot Signal Pin Name Function PIO[7]...
Page 77: Address Mapping
Chapter 4 Address Mapping Address Mapping This chapter explains the physical address map of TX4925. Please refer to “64-Bit TX System RISC TX49/H2 Core Architecture” about the details of mapping to a physical address from the virtual address of TX49/H2 core. TX4925 Physical Address Map TX4925 supports up to 4G (2 ) bytes of physical address.
Page 78: Register Map
Chapter 4 Address Mapping Register Map 4.2.1 Addressing TX4925 internal registers are to be accessed through 64 K bytes address space that is based on physical address 0xFF1F_0000 or pointed address by RAMP register (refer to 5.2.11). Figure 4.2.1 shows how to generate internal register address. Physical address 1 and physical address 2 shown Figure 4.2.1 access the same register.
Page 79: Register Map
Chapter 4 Address Mapping 4.2.3 Register Map The outline of the register map allocated built-in controllers is shown in Table 4.2.1, and the table of the internal registers is shown in Table 4.2.2, respectively. Please refer to “10.5 PCI Configuration Space Register” about PCI configuration register. Table 4.2.1 Register Map Offset Address Peripheral Controller...
Page 80 Chapter 4 Address Mapping Table 4.2.2 Internal Registers (1/8) Offset Address Register Size (bit) Register Symbol Register Name SDRAM Controller (SDRAMC) 0x8000 SDCCR0 SDRAM Channel Control Register 0 0x8004 SDCCR1 SDRAM Channel Control Register 1 0x8008 SDCCR2 SDRAM Channel Control Register 2 0x800C SDCCR3 SDRAM Channel Control Register 3...
Page 81 Chapter 4 Address Mapping Table 4.2.2 Internal Registers (2/8) DMA Controller (DMAC) 0xB000 DMCHAR0 DMA Chain Address Register 0 0xB004 DMSAR0 DMA Source Address Register 0 0xB008 DMDAR0 DMA Destination Address Register 0 0xB00C DMCNTR0 DMA Count Register 0 0xB010 DMSAIR0 DMA Source Address Increment Register 0 0xB014...
Page 82 Chapter 4 Address Mapping Table 4.2.2 Internal Registers (3/8) Offset Address Register Size (bit) Register Symbol Register Name PCI Controller (PCIC) 0xD000 PCIID ID Register (Device ID, Vendor ID) 0xD004 PCISTATUS PCI Status, Command Register (Status, Command) 0xD008 PCICCREV Class Code, Revision ID Register (Class Code, Revision ID) PCI Configuration 1 Register 0xD00C PCICFG1...
Page 83 Chapter 4 Address Mapping Table 4.2.2 Internal Registers (4/8) Offset Address Register Size (bit) Register Symbol Register Name PCI Controller (PCIC) 0xD120 G2PM0GBASE G2P Memory Space 0 G-Bus Base Address Register 0xD128 G2PM1GBASE G2P Memory Space 1 G-Bus Base Address Register 0xD130 G2PM2GBASE G2P Memory Space 2 G-Bus Base Address Register...
Page 84 Chapter 4 Address Mapping Table 4.2.2 Internal Registers (5/8) Offset Address Register Size (bit) Register Symbol Register Name Configuration 0xE000 CCFG Chip Configuration Register 0xE004 REVID Chip Revision ID Register 0xE008 PCFG Pin Configuration Register 0xE00C TOEA Timeout Error Access Address Register 0xE010 PDNCTR Power Down Control Register...
Page 85 Chapter 4 Address Mapping Table 4.2.2 Internal Registers (6/8) Offset Address Register Size (bit) Register Symbol Register Name Serial I/O (Channel 0) 0xF300 SILCR0 Line Control Register 0 0xF304 SIDICR0 DMA/Interrupt Control Register 0 0xF308 SIDISR0 DMA/ Interrupt Status Register 0 0xF30C SISCISR0 Status Change Interrupt Status Register 0...
Page 86 Chapter 4 Address Mapping Table 4.2.2 Internal Registers (7/8) Offset Address Register Size (bit) Register Symbol Register Name Interrupt Controller (IRC) 0xF510 IRFLAG0 Interrupt Request Flag 0 Register 0xF514 IRFLAG1 Interrupt Request Flag 1 Register 0xF518 IRPOL Interrupt Request Polarity Control Register 0xF51C IRRCNT Interrupt Request Control Register...
Page 87 Chapter 4 Address Mapping Table 4.2.2 Internal Registers (8/8) Offset Address Register Size (bit) Register Symbol Register Name AC-link Controller (ACLC) 0xF700 ACCTLEN ACLC Control Enable Register 0xF704 ACCTLDIS ACLC Control Disable Register 0xF708 ACREGACC ACLC CODEC Register Access Register 0xF710 ACINTSTS ACLC Interrupt Status Register...
Page 88 Chapter 4 Address Mapping 4-12...
Page 89: Configuration Register
Chapter 5 Configuration Register Configuration Register Outline The configuration registers set up and control the basic functionality of the entire TX4927. Refer to Section 5.2 for details of each configuration register. Also refer to sections mentioned in the description about each bit field. 5.1.1 Detecting G-Bus Timeout The G-Bus is an internal bus of the TX4925.
Page 90: Register
Chapter 5 Configuration Register Register Table 5.2.1 lists the configuration registers. Table 5.2.1 Configuration Register Map Reference Offset Address Size in Bits Mnemonic Register Name 5.2.1 0xE000 CCFG Chip Configuration Register 5.2.2 0xE004 REVID Chip Revision ID Register 5.2.3 0xE008 PCFG Pin Configuration Register 5.2.4...
Page 91: Chip Configuration Register (Ccfg) 0Xe000
Chapter 5 Configuration Register 5.2.1 Chip Configuration Register (CCFG) 0xE000 For the bit fields whose initial values are set by boot configuration (refer to Section 3.2), the initial input signal level and the corresponding register value are indicated. The following bits are Reserved (Read only). An explanation of the type and default was added so the default is reflected in the Boot signal.
Page 92 Chapter 5 Configuration Register Bits Mnemonic Field Name Description Timeout Enable Timeout Enable for Bus Error (Initial value: 0, R/W) for Bus Error Designates the state of the Bus Error time-out function. 0: Disable time out function. 1: Enable time out function. PCI arbiter.
Page 93: Chip Revision Id Register (Revid) 0Xe004
This field defines the minor extra code. Major Implementation Revision (Initial value: 0x1, R) MJREV Major Revision This field defines a major revision. Contact Toshiba technical staff for an explanation of the revision value. Minor Implementation Revision (Initial value: 0x1, R) MINREV Minor Revision This field defines a minor revision.
Page 94: Pin Configuration Register (Pcfg) 0Xe008
Chapter 5 Configuration Register 5.2.3 Pin Configuration Register (PCFG) 0xE008 For the bit fields whose initial values are set by boot configuration (refer to Section 3.2), the initial input signal level and the corresponding register value are indicated. SDRCLKEN PCICLKEN Reserved SELCARD SELCE...
Page 95 Chapter 5 Configuration Register Bits Mnemonic Field Name Description ACKIN ACK* input ACK* input (Initial value: 1, R/W) When this bit is one, ACK* signal is input. Refer to “7.3.6 Access Modes” for more information. 0 : ACK* pin changes from input to output dynamically based on EBUSC channel settings.
Page 96: Timeout Error Access Address Register (Toea) 0Xe00C
Chapter 5 Configuration Register 5.2.4 Timeout Error Access Address Register (TOEA) 0xE00C TOEA [31:16] : Type Undefined : Initial value TOEA [15:0] : Type Undefined : Initial value Bits Mnemonic Field Name Description 31:0 TOEA Timeout Error Timeout Error Access Address (Initial value: Undefined, R) Access Address This register latches the address on the bus when bus error occurs.
Page 97: Power Down Control Register (Pdnctr) 0Xe010
Chapter 5 Configuration Register 5.2.5 Power Down Control Register (PDNCTR) 0xE010 Reserved PDNMSK STPCPU Reserved Reserved : Type 0x3FF : Initial value PUTCV : Type 0x0000 : Initial value Bits Mnemonic Field Name Description ⎯ ⎯ Reserved Power Down Power Down Trigger (Initial value: 0, R/W) Trigger This bit is a trigger for the Power Down Sequence.
Page 98: Gbus Arbiter Priority Register (Garbp) 0Xe018
Chapter 5 Configuration Register 5.2.6 GBUS Arbiter Priority Register (GARBP) 0xE018 Reserved : Type : Initial value PRIORITY Reserved : Type 0x4688 : Initial value Bits Mnemonic Field Name Description ⎯ ⎯ 31:15 Reserved Arbitration Priority Arbitration Priority (Initial value: 0x4688, R/W) 14:0 PRIORITY This field determines the priority when GARBC.ARBMD is cleared “0”...
Page 99: Dma Request Control Register (Drqctr) 0Xe024
Chapter 5 Configuration Register 5.2.8 DMA Request Control Register (DRQCTR) 0xE024 Reserved : Type : Initial value DMAREQ[3] DMAREQ[2] DMAREQ[1] DMAREQ[0] : Type : Initial value Bits Mnemonic Field Name Description ⎯ ⎯ 31:16 Reserved DMA Request 3 (Initial value: 0x0, R/W) 15:12 DMAREQ[3] DMA Request 3...
Page 100: Clock Control Register (Clkctr) 0Xe028
Chapter 5 Configuration Register 5.2.9 Clock Control Register (CLKCTR) 0xE028 For the low-order 16 bits of the clock control register, canceling a reset requires that the corresponding reset bit be cleared by software. Before clearing them, wait at least 128 CPU clock cycles after they are set.
Page 101 Chapter 5 Configuration Register Bits Mnemonic Field Name Description PIOCKE PIO Clock PIO Clock Enable (Initial value: 1, R/W) This bit controls the PIO clock. Enable 0: Stop clock 1: Supply clock ⎯ ⎯ 15:12 Reserved PCIRSTI PCIC Reset PCIC Reset Inactive (Initial value: 1, R/W) Inactive When this bit is set to “0”, PCIC is reset.
Page 102: Gbus Arbiter Control Register (Garbc) 0Xe02C
Chapter 5 Configuration Register 5.2.10 GBUS Arbiter Control Register (GARBC) 0xE02C Reserved : Type : Initial value Reserved Reserved ARBMD Reserved : Type 0x00 1111 : Initial value Bits Mnemonic Field Name Description ⎯ ⎯ 31:13 Reserved ⎯ 12:5 Reserved Note: This bit is always set to “0”...
Page 103: Clocks
Chapter 6 Clocks Clocks TX4925 Clock Signals Figure 6.1.1 shows the configuration of TX4925 blocks and clock signals. Table 6.1.1 describes each clock signal. Table 6.1.2 shows the relationship among different clock signals when the CPU clock frequency is 200 MHz. PCICLK[2:1] PCICLK_IO SYSCLK...
Page 104 Chapter 6 Clocks Table 6.1.1 TX4925 Clock Signals (1/2) Related Related Registers Input/ Clock Description Configuration Signals (Refer to Chapters 5 Output (Refer to Section 3.2) and 10.) ⎯ ⎯ MASTERCLK Input Master input clock for the TX4925. The TX4925 internal clock generator multiplies or divides MASTERCLK to generate internal clock pulses.
Page 105 Chapter 6 Clocks Table 6.1.1 TX4925 Clock Signals (2/2) Related Related Registers Input/ Clock Description Configuration Signals (Refer to Chapters 5 Output (Refer to Section 3.2) and 10.) ⎯ SDCLK[1:0] Output Clock supplied to SDRAM. The frequency of PCFG.SDCLKEN [1:0] SDCLK[1:0] is the same as that of GBUSCLK.
Page 106 Chapter 6 Clocks Table 6.1.2 Relationship Among Different Clock Frequencies Input Clock Internal Clock External Clock (Output) SYSCLK (MHz) SDCLK PCICLK[2:1], Boot Configuration MASTERCLK CPUCLK GBUSCLK IMBUSCLK GBUSCLKF IMBUSCLKF RF Setting [1:0] PCICLK_IO Setting (MHz) (MHz) (MHz) (MHz) (MHz) (MHz) (MHz) (MHz) ADDR[4:3]...
Page 107: Power-Down Mode
Chapter 6 Clocks Power-Down Mode 6.2.1 Halt Mode and Doze Mode The WAIT instruction causes the TX49/H2 core to enter either of the two low-power modes: Halt and Doze. The TX49/H2 can exit from Halt or Doze mode upon an interrupt exception. Ensure, therefore, that the TX49/H2 does not enter Halt or Doze mode when all interrupts are masked in the interrupt controller.
Page 108: Power-On Sequence
Chapter 6 Clocks Power-On Sequence MASTERCLK stable time MASTERCLK RESET* width time RESET* PON* PON* PLL stable time width time PLL output CPUCLK GBUSCLK PCICLK Figure 6.3.1 Power-On Sequence...
Page 109: External Bus Controller
Chapter 7 External Bus Controller External Bus Controller Features The External Bus Controller is used for accessing ROM, SRAM memory, and I/O peripherals. The features of this bus are described below. • 8 independent channels (Channel 6 and 7 are used only PCMCIA mode.) •...
Page 110: Block Diagram
Chapter 7 External Bus Controller Block Diagram External Bus Controller (EBUSC) G-Bus Channel Control CE*[5:0] G-Bus I/F Register SWE* ACEHOLD Register Address Address BWE*[3:0]/BE*[3:0] Decoder Decoder Timing Boot Control ACK*/READY Options Host I/F Timing Control CARDREG* CARDDIR* Channel Control CARD1CSH/L*,CARD2CSH/L* Register CARDIORD* CARDIOWR*...
Page 111: Detailed Explanation
Chapter 7 External Bus Controller Detailed Explanation 7.3.1 External Bus Control Register The External Bus Controller (EBUSC) has eight channels. This register contains one Channel Control Register (EBCCRn) for each channel, and all settings can be made independently for each channel. However channel 6 and 7 are used only PCMCIA mode because TX4925 hasn’t CE[7:6] signals.
Page 112: Global/Boot-Up Options
Chapter 7 External Bus Controller 7.3.2 Global/Boot-up Options In addition to the settings made separately for each channel, the Channel Control Registers can also use global options that make settings common to all channels. External Bus Controller Channel 0 and 7 can be used as a Boot memory channel. Channel 0 and 7 is set by the external pins (Boot pins) during reset.
Page 113: Address Mapping
Chapter 7 External Bus Controller 7.3.3 Address Mapping Each of the eight channels can use the Base Address field (EBBAR.BA[31:20]) and the Channel Size field (EBCCRn.CS[3:0]) of the External Bus Channel Control Register to map to any physical address. A channel is selected when the following equation becomes True. paddr[31:20] &...
Page 114: External Address Output
Chapter 7 External Bus Controller 7.3.4 External Address Output The maximum memory space size for each channel is 1 GB (230B). Addresses are output by dividing the 20-bit ADDR[19:0] signal into two parts: the upper address and the lower address. The address bit output to each bit of the ADDR[19:0] signal changes according to the setting of the channel data bus width.
Page 115: Data Bus Size
Chapter 7 External Bus Controller 7.3.5 Data Bus Size The External Bus Controller supports devices with a data bus width of 8 bits, 16 bits, and 32 bits. The data bus width is selected using the BSZ field of the Channel Control Register (EBCCRn). The address bits output to each bit of the ADDR[19:0] signal change according to the mode.
Page 116 Chapter 7 External Bus Controller 7.3.5.3 8-bit Bus Width Mode DATA[7:0] becomes valid. Bits [19:0] of the physical address are output to ADDR[19:0]. The internal address bits [27:20], which are the upper address, are multiplexed to external ADDR[19:12]. In other words, the address is shifted up two bits or more relative to the 32-bit bus mode when output.
Page 117: Access Modes
Chapter 7 External Bus Controller 7.3.6 Access Modes The following four modes are available as controller access modes. These modes can be set separately for each channel. • Normal mode • Page mode • External ACK mode • Ready mode Depending on the combination of modes in each channel, either of two modes in which the ACK*/Ready signal operates differently (ACK*/Ready Dynamic mode, ACK*/Ready Static mode) is selected by the ACK*/Ready Mode bit (PCFG.ACKIN) of the Chip Configuration Register.
Page 118 Chapter 7 External Bus Controller 7.3.6.1 Normal Mode When in this mode, the ACK*/Ready signal becomes an ACK* output when it is in the ACK*/Ready Dynamic mode. The ACK*/Ready signal becomes High-Z when it is in the ACK*/Ready Static mode. Wait cycles are inserted according to the EBCCRn.PWT and EBCCRn.WT value at the access cycle.
Page 119 Chapter 7 External Bus Controller 7.3.6.3 Ready Mode When in this mode, the ACK*/Ready pin becomes Ready input, and the cycle is ended by Ready input from an external device. Ready input is internally initialized. See Section “7.3.7.5 Ready Input Timing” for more information regarding the operation timing. When the Wait cycle count specified by EBCCREBCCRn.PWT:WT elapses, a check is performed to see whether the Ready signal was asserted.
Page 120 Chapter 7 External Bus Controller 7.3.6.4 Page Mode When in this mode, the ACK*/Ready pin becomes ACK* output when it is in the Dynamic mode. When it is in the ACK*/Ready Static mode, the ACK*/Ready signal becomes High-Z. Wait cycles are inserted into the access cycle according to the values of EBCCRn.PWT and EBCCRn.WT.
Page 121: Access Timing
Chapter 7 External Bus Controller 7.3.7 Access Timing 7.3.7.1 SHWT Option The SHWT option is selected when the SHWT (Setup/Hold Wait Time) field of the Channel Control Register is a value other than “0”. This option inserts a Setup cycle and a Hold cycle between the current signal and the next signal.
Page 122 Chapter 7 External Bus Controller 7.3.7.2 ACK*/READY Input/Output Switching Timing When in the ACK*/Ready Static mode, the ACK*/Ready signal is always an input signal. When in the ACK*/Ready Dynamic mode, the ACK*/Ready signal is an input signal when in the External ACK mode or the Ready mode, but is an output signal in all other modes.
Page 123 Chapter 7 External Bus Controller 7.3.7.4 ACK* Input Timing (External ACK Mode) The ACK* signal becomes an input signal when in the external ACK mode. During a Read cycle, data latched timing is selectable from two cases by EBCCRn.LDEA bit. When EBCCRn.LDEA is zero, data is latched two clock cycles after assertion of the ACK* signal is acknowledged (Figure 7.3.9 ACK* Input Timing (Single Read Cycle)).
Page 124 Chapter 7 External Bus Controller SYSCLK ADDR [19:0] DATA [31:0] ACK*/READY (Input) Latch Data Acknowledge ACK* EBCCRn.SHWT=0 EBCCRn.LDEA=1 Figure 7.3.10 ACK* Input Timing (Single Read Cycle) SYSCLK ADDR [19:0] 3 clocks SWE*/BWE* DATA [31:0] 4 clocks ACK*/READY (Input) Acknowledge ACK* EBCCRn.SHWT=0 Figure 7.3.11 ACK* Input Timing (Single Write Cycle) 7-16...
Page 125 Chapter 7 External Bus Controller SYSCLK ADDR [19:0] DATA [31:0] ACK*/READY (Input) 2 clocks clocks Latch Latch Acknowledge Acknowledge Data Data ACK* ACK* EBCCRn.SHWT=0 Figure 7.3.12 ACK* Input Timing (Burst Read Cycle) SYSCLK ADDR [19:0] 3 clocks 3 clocks SWE*/BWE* 4 clocks 4 clocks DATA [31:0]...
Page 126 Chapter 7 External Bus Controller 7.3.7.5 Ready Input Timing The ACK*/Ready pin is used as a Ready input when in the Ready mode. The Ready input timing is the same as the ACK* input timing explained in “7.3.7.4 ACK* Input Timing (External ACK Mode)”...
Page 127: Clock Options
Chapter 7 External Bus Controller SYSCLK ADDR [19:0] 3 clock SWE*/BWE* DATA [31:0] 4 clock ACK*/READY (Input) Acknowledge Read EBCCRn.PWT:WT = 2 EBCCRn.SHWT = 0 SYSCLK ADDR [19:0] 3 clock SWE*/BWE* DATA [31:0] 4 clock ACK*/READY (Input) Acknowledge Read Start Ready Check EBCCRn.PWT:WT = 2 EBCCRn.SHWT = 0...
Page 128: Pcmcia Mode
Chapter 7 External Bus Controller 7.3.9 PCMCIA mode The EBUSC Controller supports the following functions of the 16-Bit PC Card interface. The EBUSC Controller supports 2 PCMCIA slots. Any of the eight EBUSC Controller channels can target the 2 PCMCIA slots. The use of channels 6 and 7 first for PCMCIA is recommended, since their normal CE_ signals are not pinned out and they cannot be used for any other function.
Page 129 Chapter 7 External Bus Controller 7.3.9.3 PCMCIA Channel Programming Requirements Because of the multiple modes possible on a given EBUSC Channel the following restrictions apply when a channel is used for PCMCIA access. Page Mode is not allowed on a PCMCIA enabled Channel. Undetermined results will occur if Page Mode is active.
Page 130 Chapter 7 External Bus Controller 7.3.9.6 PCMCIA Cycle Types Burst Cycles are not allowed on a PCMCIA enabled Channel. This is due to the fact that the EBUSC Controller does not toggle all signals between the individual accesses for burst accesses. The PCMCIA specification requires that all signals toggle per each access.
Page 131 Chapter 7 External Bus Controller Table 7.3.10 Access Mapping (PCMCIA in 16-bit Channel and Big Endian Mode) CARDnCSH*, Access Access ADDR[1:0] Port Size DATA[15:8] DATA[7:0] Address CARDnCSL* Word(1/2) 16-bit R[31:24] R[23:16] Word{2/2} 16-bit R[15:8] R[7:0] Triple byte(1/2) 16-bit R[31:24] R[23:16] Triple byte(2/2) 16-bit R[15:8]...
Page 132: Register
Chapter 7 External Bus Controller Register Table 7.4.1 External Bus Controller (EBUSC) Registers Reference Offset Address Bit Width Register Symbol Register Name 7.4.1 0x9000 EBCCR0 External Bus Channel Control Register 0 7.4.2 0x9004 EBBAR0 External Bus Base Address Register 0 7.4.1 0x9008 EBCCR1...
Page 133: External Bus Channel Control Register (Ebccrn) 0X9000 (Ch. 0), 0X9008 (Ch. 1)
Chapter 7 External Bus Controller 7.4.1 External Bus Channel Control Register (EBCCRn) 0x9000 (ch. 0), 0x9008 (ch. 1) 0x9010 (ch. 2), 0x9018 (ch. 3) 0x9020 (ch. 4), 0x9028 (ch. 5) 0x9030 (ch. 6), 0x9038 (ch. 7) Channel 0 and 7 can be used as Boot memory. Therefore, the default is set by the Boot signal (see “7.3.2 Global/Boot-up Options”).
Page 134 Chapter 7 External Bus Controller Bits Mnemonic Field Name Description 26:24 PCMCIA 16-bit PCMCIA 16-bit PC Card Mode (Initial value: 000(ch0-6)/001(ch7), R/W) PC Card Mode Specifies the PCMCIA mode. 000 : PCMCIA Disabled for Channel. 001 : PCMCIA Common Memory Access Enabled for Channel. 010 : PCMCIA IO Access Enabled for Channel.
Page 135 Chapter 7 External Bus Controller Bits Mnemonic Field Name Description 11:8 Channel Size External Bus Control Channel Size (Initial value: 0010(ch0,7)/0000(ch1-6), R/W) Specifies the channel memory size. 0000: 1 MB 0101: 32 MB *1010: 1 GB 0001: 2 MB 0110: 64 MB 1011-1111: Reserved 0010: 4 MB 0111: 128 MB...
Page 136: External Bus Base Address Register (Ebbarn) 0X9000 (Ch. 0), 0X9008 (Ch. 1) 0X9010 (Ch. 2), 0X9018 (Ch. 3) 0X9020 (Ch. 4), 0X9028 (Ch. 5) 0X9030 (Ch. 6), 0X9038 (Ch. 7)
Chapter 7 External Bus Controller 7.4.2 External Bus Base Address Register (EBBARn) 0x9000 (ch. 0), 0x9008 (ch. 1) 0x9010 (ch. 2), 0x9018 (ch. 3) 0x9020 (ch. 4), 0x9028 (ch. 5) 0x9030 (ch. 6), 0x9038 (ch. 7) Channel 0 can be used as Boot memory. Therefore, the default is set by the Boot signal (see “7.3.2 Global/Boot-up Options”).
Page 137: Timing Diagrams
Chapter 7 External Bus Controller Timing Diagrams Please take the following points into account when referring to the timing diagrams. (1) The clock frequency of the SYSCLK signal can be set to one of the following divisions of the internal bus clock (GBUSCLK): 1/1, 1/2, 1/3, or 1/4.
Page 138: Uae Signal
Chapter 7 External Bus Controller 7.5.1 UAE Signal Figure 7.5.1 UAE Signal (CCFG.ACEHOLD=1, PWT: WT=0, SHWT=0, Normal) 7-30...
Page 139 Chapter 7 External Bus Controller Figure 7.5.2 UAE Signal (CCFG.ACEHOLD=0, PWT: WT=0, SHWT=0, Normal) 7-31...
Page 140: Normal Mode Access (Single, 32-Bit Bus)
Chapter 7 External Bus Controller 7.5.2 Normal Mode Access (Single, 32-bit Bus) Figure 7.5.3 Double-word Single Write (PWT: WT=0, SHWT=0, Normal, 32-bit Bus) 7-32...
Page 141 Chapter 7 External Bus Controller SYSCLK ADDR[19:0] BUSSPRT* SWE* BWE* DATA[31:0] ACK* Figure 7.5.4 Double-word Single Read (PWT: WT=0, SHWT=0, Normal, 32-bit Bus) 7-33...
Page 142 Chapter 7 External Bus Controller Figure 7.5.5 1-word Single Write (PWT: WT=1, SHWT=0, Normal, 32-bit Bus) 7-34...
Page 143 Chapter 7 External Bus Controller Figure 7.5.6 1-word Single Read (PWT: WT=1, SHWT=0, Normal, 32-bit Bus) 7-35...
Page 144: Normal Mode Access (Burst, 32-Bit Bus)
Chapter 7 External Bus Controller 7.5.3 Normal Mode Access (Burst, 32-bit Bus) Figure 7.5.7 4-word Burst Read (PWT: WT=1, SHWT=0, Normal, 32-bit Bus) 7-36...
Page 145 Chapter 7 External Bus Controller SYSCLK ADDR[19:0] BUSSPRT* SWE* BWE* DATA[31:0] ACK* Figure 7.5.8 4-word Burst Read (PWT: WT=1, SHWT=0, Normal, 32-bit Bus) 7-37...
Page 146: Normal Mode Access (Single, 16-Bit Bus)
Chapter 7 External Bus Controller 7.5.4 Normal Mode Access (Single, 16-bit Bus) Figure 7.5.9 Double-word Single Write (PWT: WT=0, SHWT=0, Normal, 16-bit Bus) 7-38...
Page 147 Chapter 7 External Bus Controller Figure 7.5.10 Double-word Single Read (PWT: WT=0, SHWT=0, Normal, 16-bit Bus) 7-39...
Page 148 Chapter 7 External Bus Controller Figure 7.5.11 Half-word Single Write (PWT: WT=0, SHWT=0, Normal, 16-bit Bus) 7-40...
Page 149 Chapter 7 External Bus Controller Figure 7.5.12 Half-word Single Read (PWT: WT=0, SHWT=0, Normal, 16-bit Bus) 7-41...
Page 150: Normal Mode Access (Burst, 16-Bit Bus)
Chapter 7 External Bus Controller 7.5.5 Normal Mode Access (Burst, 16-bit Bus) Figure 7.5.13 4-word Burst Read (PWT: WT=0, SHWT=0, Normal, 16-bit Bus) 7-42...
Page 151 Chapter 7 External Bus Controller Figure 7.5.14 4-word Burst Write (PWT: WT=0, SHWT=0, Normal, 16-bit Bus) 7-43...
Page 152: Normal Mode Access (Single, 8-Bit Bus)
Chapter 7 External Bus Controller 7.5.6 Normal Mode Access (Single, 8-bit Bus) Figure 7.5.15 Double-word Single Write (PWT: WT=0, SHWT=0, Normal, 8-bit Bus) 7-44...
Page 153 Chapter 7 External Bus Controller Figure 7.5.16 Double-word Single Read (PWT: WT=0, SHWT=0, Normal, 8-bit Bus) 7-45...
Page 154 Chapter 7 External Bus Controller SYSCLK ADDR [19:0] OE*/BUSSPRT* SWE* BWE* DATA [7:0] ACK* Figure 7.5.17 1-byte Single Write (PWT: WT=1, SHWT=0, Normal, 8-bit Bus) SYSCLK ADDR [19:0] BUSSPRT SWE* BWE* DATA [7:0] ACK* Figure 7.5.18 1-byte Single Read (PWT: WT=1, SHWT=0, Normal, 8-bit Bus) 7-46...
Page 155: Normal Mode Access (Burst, 8-Bit Bus)
Chapter 7 External Bus Controller 7.5.7 Normal Mode Access (Burst, 8-bit Bus) Figure 7.5.19 4-word Burst Write (PWT: WT=0, SHWT=0, Normal, 8-bit Bus) 7-47...
Page 156 Chapter 7 External Bus Controller Figure 7.5.20 4-word Burst Read (PWT: WT=0, SHWT=0, Normal, 8-bit Bus) 7-48...
Page 157: Page Mode Access (Burst, 32-Bit Bus)
Chapter 7 External Bus Controller 7.5.8 Page Mode Access (Burst, 32-bit Bus) Figure 7.5.21 8-word Burst Write (WT=1, PWT=0, SHWT=0, 4-page, 32-bit Bus) 7-49...
Page 158 Chapter 7 External Bus Controller Figure 7.5.22 4-word Burst Read (WT=2, PWT=1, SHWT=0, 4-page, 32-bit Bus) 7-50...
Page 159: External Ack Mode Access (32-Bit Bus)
Chapter 7 External Bus Controller 7.5.9 External ACK Mode Access (32-bit Bus) SYSCLK ADDR[19:0] OE*/BUSSPRT* SWE* BWE* DATA[31:0] ACK* Note 1: The TX4925 sets the ACK* signal to High Impedance in the S1 State. Note 2: External devices drive the ACK* signal to Low (assert the signal) until the ES1 State.
Page 160 Chapter 7 External Bus Controller Figure 7.5.25 4-word Burst Write (0 Wait, SHWT=0, External ACK*, 32-bit Bus) 7-52...
Page 161 Chapter 7 External Bus Controller Figure 7.5.26 4-word Burst Read (0 Wait, SHWT=0, External ACK*, 32-bit Bus) 7-53...
Page 162 Chapter 7 External Bus Controller Figure 7.5.27 Double-word Single Write (1 Wait, SHWT=2, External ACK*, 32-bit Bus) 7-54...
Page 163 Chapter 7 External Bus Controller Figure 7.5.28 Double-word Single Read (0 Wait, SHWT=2, External ACK*, 32-bit Bus) 7-55...
Page 164 Chapter 7 External Bus Controller AS2 CS1 CS2 SW1 ES1 CH1 CH2 AH1 AH2 SYSCLK ADDR[19:0] OE*/BUSSPRT* SWE* BWE* DATA[31:0] ACK* Figure 7.5.29 1-word Single Write (1 Wait, SHWT=2, External ACK*, 32-bit Bus) AS2 CS1 CH1 CH2 AH1 AH2 SYSCLK ADDR[19:0] BUSSPRT* SWE*...
Page 165: Ready Mode Access (32-Bit Bus)
Chapter 7 External Bus Controller 7.5.10 READY Mode Access (32-bit Bus) Figure 7.5.31 1-word Single Write (PWT: WT=2, SHWT=1, READY, 32-bit Bus) 7-57...
Page 166 Chapter 7 External Bus Controller Figure 7.5.32 1-word Single Read (PWT: WT=2, SHWT=1, READY, 32-bit Bus) 7-58...
Page 167: Flash Rom, Sram Usage Example
Chapter 7 External Bus Controller Flash ROM, SRAM Usage Example Figure 7.6.1 illustrates example Flash ROM connections, and Figure 7.6.2 illustrates example SRAM connections. Also, Figure 7.6.3 illustrates example connections with the SDRAM and the bus separated. Since connecting multiple memory devices such as SDRAM and ROM onto a single bus increases the load, 100 MHz class high-speed SDRAM access may not be performed normally.
Page 168 Chapter 7 External Bus Controller TX4925 SDRAM (x16 Bits) DQM[3] DQM[2] DQM[1] DQM[0] DQM[7:0] ADDR[19:16] UDQM LDQM UDQM LDQM SADDR10 ADDR[14:5] ADDR[19:16], A[12:0] A[12:0] ADDR[19] SADDR10, ADDR[18] ADDR[14:5] SDCS[0]* RAS* RAS* RAS* CAS* CAS* CAS* SDCLKIN SDCLK[0] DQ[15:0] DQ[15:0] D[31:16] D[15:0] DATA[31:0] Flash ROM (x16 Bits)
Page 169: Dma Controller
Chapter 8 DMA Controller DMA Controller Features The TX4925 contains a four-channel DMA Controller (DMAC) that executes DMA (Direct Memory Access) with memory and I/O devices. The DMA Controller has the following characteristics. • Has four on-chip DMA channels • Supports external I/O devices with 8-, 16-, and 32-bit Data Bus widths and transfer between memory devices.
Page 170: Block Diagram
Chapter 8 DMA Controller Block Diagram DMAREQ[0] DMAC DMCHAR0 External DREQ0 Pins Channel 0 DMSAR0 DMAACK[0] DMDAR0 DACK0 DMCNTR0 Internal DMSAIR0 Control DMMCR DMDAIR0 Block DMCCR0 DMMFDR PCFG.DMASEL0 DMCSR0 G-Bus DMAREQ[1] DMCHAR1 External DREQ1 Pins Channel 1 DMSAR1 DMAACK[1] DMDAR1 DACK1 DMCNTR1 Internal...
Page 171: Detailed Explanation
Chapter 8 DMA Controller Detailed Explanation 8.3.1 Transfer Mode The DMA Controller supports five transfer mode types (refer to Table 8.3.1 below). The setting of the External Request bit (DMCCRn.EXTRQ) of the DMA Channel Control Register selects whether transfer with an I/O device is a DMA transfer. •...
Page 172: External I/O Dma Transfer Mode
Chapter 8 DMA Controller 8.3.3 External I/O DMA Transfer Mode The External I/O DMA Transfer Mode performs DMA transfer with external I/O devices that are connected to the External Bus Controller. 8.3.3.1 External Interface External I/O devices signal DMA requests to the DMA Controller by asserting the DMA Transfer Request Signal (DMAREQ[n]).
Page 173 Chapter 8 DMA Controller SYSCLK ADDR [19:0] 1c040 00040 ACE* OE*/BUSSPRT* SWE* BWE* DATA [31:0] 00000100 ACK* 1 cycle DMAREQ[n] DMAACK[n] DMADONE* Figure 8.3.1 External I/O DMA Transfer (Single Address, Level Request) 8.3.3.2 Dual Address Transfer If the Single Address bit (DMCCRn.SNGAD) has been cleared, access to external I/O devices and to external memory is each performed continuously.
Page 174 Chapter 8 DMA Controller • Single Address transfer from memory to an external I/O device (DMCCRn.MEMIO = “0”) External memory Write operation to an address specified by the DMA Source Address Register (DMSARn) is performed simultaneously to assertion of the DMAACK[n] signal. At this time, the external I/O device drives the DATA signal instead of the TX4925.
Page 175: Internal I/O Dma Transfer Mode
Chapter 8 DMA Controller When the Chain End bit (CHDN) is cleared, only DMA transfer specified by the current DMA Channel Register ends normally, and only the Normal Transfer End bit (NTRNFC) is set. When the Chain Enable bit (CHNEN) of the DMA Channel Control Register (DMCCRn) is set, chain transfer is executed and DMA transfer continues.
Page 176: Memory Fill Transfer Mode
Chapter 8 DMA Controller 8.3.6 Memory Fill Transfer Mode When in the Memory Fill Transfer mode, word data set in the DMA Memory Fill Data Register (DMMFDR) is written to the data region specified by the DMA Source Address Register (DMSARn). This data can be used for initializing the memory, etc.
Page 177 Chapter 8 DMA Controller During Single Address transfer, the DMA Destination Address Register (DMDARn) and DMA Destination Address Increment Register (DMDAIRn) settings are ignored. Table 8.3.2 Channel Register Setting Restrictions During Single Address Transfer DMSARn[1:0] Transfer Setting Size DMSAIRn[1:0] DMCNTRn[1:0] DMSAIRn is “0”...
Page 178: Dual Address Transfer
Chapter 8 DMA Controller 3 Words 4 Words 4 Words 4 Words 4 Words (3 + 1) Words 32 Word Boundary 4 Words 4 Words 4 Words 4 Words 4 Words 4 Words DMCCRn.XFSZ = 0x4 DMCCRn. XFSZ = 0x4 (a) DMCCRn.USEXFSZ = “0”...
Page 179 Chapter 8 DMA Controller Example: When the transfer address is 0x0001_0000, the DMA Source Address Register (DMSARn) is as follows below. • DMSAIRn setting is “0” or greater: 0x0001_0000 • DMSAIRn setting is a negative value: 0x0001_0003 Table 8.3.3 Channel Register Setting Restrictions During Dual Address Transfer DMSARn[1:0] DMDARn[1:0] Transfer Setting...
Page 180 Chapter 8 DMA Controller Source Address FIFO (8 Words) Destination Address Figure 8.3.3 Dual Address Burst Transfer (DMCCRn.USEXFSZ = 1) Figure 8.3.4 shows Dual Address Burst transfer when the Transfer Size Mode bit (DMCCRn.USEXFSZ) is set to “0”, the lower 7 bits of the Transfer Start address for the transfer source are set to 0x54, the lower 7 bits of the Transfer Start address for the transfer destination are set to (a) 0x14/(b) 0x18, and the Transfer Setting Size (DMCCRn.XFSZ) is set to 8 words.
Page 181 Chapter 8 DMA Controller When the Destination Burst Inhibit bit (DMCCRn.DBINH) is set, data written from the FIFO to the Destination Address is divided into multiple 4-byte Single Write transfers, then transfer is executed. Only 4, 0 and 4 can be set on Burst Inhibit bit during Burst transfer. When the Burst Inhibit bit is set, an any multiples of 4 can be set.
Page 182 Chapter 8 DMA Controller Source Address FIFO (8 Double Words) Destination Address (a) Address offset is equivalent (b) Address offset differs Figure 8.3.4 Dual Address Burst Transfer (DMCCRn.USEXFSZ = 0) 8-14...
Page 183: Dma Transfer
Chapter 8 DMA Controller 8.3.9 DMA Transfer The sequence of DMA transfer that uses only the DMA Channel Register is as follows below. (1) Select DMA request signal To perform external I/O or internal I/O DMA, set the DMA Request Select field of the DMA Request Control Register (DRQCTR.
Page 184: Chain Dma Transfer
Chapter 8 DMA Controller 8.3.10 Chain DMA Transfer Table 8.3.4 shows the data structure in memory that the DMA Command Descriptor has. When the Simple Chain bit (SMPCHN) of the DMA Channel Control Register (DMCCRn) is set, only the initial four words are used.
Page 185 Chapter 8 DMA Controller The sequence of Chain DMA transfer is as follows below. (1) Select DMA request signal To perform external I/O or internal I/O DMA, set the DMA Request Select field of the DMA Request Control Register (DRQCTR. DMAREQ). For external I/O DMA, also program the function of the shared pin through the DMA Select field of the Pin Configuration Register (PCFG.SELDMA).
Page 186: Dynamic Chain Operation
Chapter 8 DMA Controller (8) Signal completion Set the Normal Chain End bit (NCHNC) of the DMA Channel Status Register (DMCSRn) when DMA data transfer of all Descriptor Chains is complete. An interrupt is signalled if the Chain End Interrupt Enable bit (INTENC) of the DMA Channel Control Register (DMCCRn) is set at this time.
Page 187: Interrupts
Chapter 8 DMA Controller 8.3.12 Interrupts An interrupt number (10 – 13) of the Interrupt Controller is mapped to each channel. In addition, there are completion interrupts for when transfer ends normally and error interrupts for when transfer ends abnormally for each channel. When an interrupt occurs, then the bit that corresponds to either the Normal Interrupt Status field (DIS[3:0]) or the Error Interrupt Status field (EIS[3:0]) of the DMA Master Control Register (DMMCR) is set.
Page 188: Arbitration Among Dma Channels
Chapter 8 DMA Controller 8.3.14 Arbitration Among DMA Channels The DMA Controller has an on-chip DMA Channel Arbiter that arbitrates bus ownership among four DMA channels that use the internal bus (G-Bus). There are two methods for determining priority: the round robin method and the fixed priority method.
Page 189: Registers
Chapter 8 DMA Controller Registers Table 8.4.1 DMA Controller Registers Reference Offset Address Bit Width Mnemonic Register Name 8.4.6 0xB000 DMCHAR0 DMA Chain Address Register 0 8.4.4 0xB004 DMSAR0 DMA Source Address Register 0 8.4.5 0xB008 DMDAR0 DMA Destination Address Register 0 8.4.9 0xB00C DMCNTR0...
Page 190: Dma Master Control Register (Dmmcr) 0Xb0A8
Chapter 8 DMA Controller 8.4.1 DMA Master Control Register (DMMCR) 0xB0A8 This register controls the entire DMA Controller. EIS[3:0] DIS[3:0] Reserved FIFOVC : Type 0000 0000 000000 : Initial value FIFVC FIFWP FIFRP FIFUM[3:0] RSFIF RRPT Reserved MSTEN R/W : Type 0000 : Initial value Bits...
Page 191 Chapter 8 DMA Controller Mnemonic Field Name Description FIFUM[3:0] FIFO Use Enable FIFO Use Enable [3:0] (Initial value: 0x0, R/W) [3:0] Each channel specifies whether to use 8 -word FIFO in Dual Address transfer. FIFUM[n] corresponds to channel n. Refer to “8.3.8.2 Burst Transfer During Dual Address Transfer” for more information. ⎯...
Page 192: 0Xb058 (Ch. 2) 0Xb078 (Ch. 3)
Chapter 8 DMA Controller 8.4.2 DMA Channel Control Register (DMCCRn) 0xB018 (ch. 0) 0xB038 (ch. 1) 0xB058 (ch. 2) 0xB078 (ch. 3) Reserved DNCTL IMMCHN DBINH SBINH CHRST RVBYTE ACKPOL REQPL EGREQ CHDN EXTRQ USEXFSZ R/W : Type : Initial value STLTIME/INTRQD Reserved XFSZ...
Page 193 Chapter 8 DMA Controller Bits Mnemonic Field Name Description DBINH Destination Burst Destination Burst Inhibit (Initial value: 0, R/W) Inhibit During Dual Address transfer, this bit sets whether to perform Burst transfer or Single transfer on a Write cycle to the address set from FIFO to DMDARn when Burst transfer is set by DMCCRn.XFSZ.
Page 194 Chapter 8 DMA Controller Bits Mnemonic Field Name Description EXTRQ External Request External Request (Initial value: 0, R/W) Sets the Request Transfer mode. 1: I/O DMA transfer mode This bit is used by the External I/O DMA Transfer mode and the Internal I/O DMA Transfer mode.
Page 195 Chapter 8 DMA Controller Bits Mnemonic Field Name Description CHNEN Chain Enable Chain Enable (Initial value: 0, R) This bit indicates whether Chain operation is being performed. Read Only. This bit is cleared when either the Master Enable bit (DMMCR.MSTEN) is cleared or the Channel Reset bit (DMCCRn.CHRST) is set.
Page 196: Dma Channel Status Register (Dmcsrn) 0Xb01C (Ch. 0) 0Xb03C (Ch. 1) 0Xb05C (Ch. 2) 0Xb07C (Ch. 3)
Chapter 8 DMA Controller 8.4.3 DMA Channel Status Register (DMCSRn) 0xB01C (ch. 0) 0xB03C (ch. 1) 0xB05C (ch. 2) 0xB07C (ch. 3) WAITC : Type : Initial value 0x0000 Reserved CHNEN XFACT ABCHC NCHNC EXTDN CFERR CHERR NTRNFC DESERR SORERR STLXFER R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C : Type...
Page 197 Chapter 8 DMA Controller Bits Mnemonic Field Name Description XFACT Transfer Active Transfer Active (Initial value: 0, R) This value is a copy of the Transfer Active bit (XFACT) of the DMA Channel Control Register (DMCCRn). ABCHC Error Complete Error Completion (Initial value: 0, R) This bit indicates whether an error occurred during DMA transfer.
Page 198: 0Xb044 (Ch. 2) 0Xb064 (Ch. 3)
Chapter 8 DMA Controller 8.4.4 DMA Source Address Register (DMSARn) 0xB004 (ch. 0) 0xB024 (ch. 1) 0xB044 (ch. 2) 0xB064 (ch. 3) SADDR[31:16] : Type : Initial value SADDR[15:0] : Type : Initial value Bits Mnemonic Field Name Description 31:0 SADDR Source Address Source Address (Initial value: undefined, R/W)
Page 199: 0Xb048 (Ch. 2) 0Xb068 (Ch. 3)
Chapter 8 DMA Controller 8.4.5 DMA Destination Address Register (DMDARn) 0xB008 (ch. 0) 0xB028 (ch. 1) 0xB048 (ch. 2) 0xB068 (ch. 3) DADDR[31:16] : Type : Initial value DADDR[15:0] : Type : Initial value Bits Mnemonic Field Name Description Destination 31:0 DADDR Destination Address (Initial value: undefined, R/W)
Page 200: 0Xb040 (Ch. 2) 0Xb060 (Ch. 3)
Chapter 8 DMA Controller 8.4.6 DMA Chain Address Register (DMCHARn) 0xB000 (ch. 0) 0xB020 (ch. 1) 0xB040 (ch. 2) 0xB060 (ch. 3) CHADDR[31:16] : Type : Initial value CHADDR[15:3] Reserved : Type : Initial value Bits Mnemonic Field Name Description 31:2 CHADDR Chain Address...
Page 201: Dma Source Address Increment Register (Dmsairn) 0Xb010 (Ch. 0) 0Xb030 (Ch. 1)
Chapter 8 DMA Controller 8.4.7 DMA Source Address Increment Register (DMSAIRn) 0xB010 (ch. 0) 0xB030 (ch. 1) 0xB050 (ch. 2) 0xB070 (ch. 3) Reserved SADINC[23:16] : Type : Initial value SADINC[15:0] : Type : Initial value Bits Mnemonic Field Name Description ⎯...
Page 202: 0Xb054 (Ch. 2) 0Xb074 (Ch. 3)
Chapter 8 DMA Controller 8.4.8 DMA Destination Address Increment Register (DMDAIRn) 0xB014 (ch. 0) 0xB034 (ch. 1) 0xB054 (ch. 2) 0xB074 (ch. 3) Reserved DADINC[23:16] : Type : Initial value DADINC[15:0] : Type : Initial value Bits Mnemonic Field Name Description ⎯...
Page 203: 0Xb04C (Ch. 2) 0Xb06C (Ch. 3)
Chapter 8 DMA Controller 8.4.9 DMA Count Register (DMCNTRn) 0xB00C (ch. 0) 0xB02C (ch. 1) 0xB04C (ch. 2) 0xB06C (ch. 3) Reserved DMCNTR[25:16] : Type : Initial value DMCNTR[15:0] : Type : Initial value Bits Mnemonic Field Name Description ⎯ ⎯...
Page 204: Dma Memory Fill Data Register (Dmmfdr) 0Xb0A4
Chapter 8 DMA Controller 8.4.10 DMA Memory Fill Data Register (DMMFDR) 0xB0A4 : Type : Initial value : Type : Initial value Bits Mnemonic Field Name Description 31:0 Memory Fill Data Memory Fill Data (Initial value: undefined, R/W) This register, which stores word data written to memory when in the Memory Fill Transfer mode, is shared between all channels.
Page 205: Timing Diagrams
Chapter 8 DMA Controller Timing Diagrams This section contains timing diagrams for the external I/O DMA transfer mode. The DMAREQ[n] signals and DMAACK[n] signals in the timing diagrams are set to Low Active. 8.5.1 Single Address Single Transfer from Memory to I/O (32-bit ROM) SYSCLK ADDR [19:0] 1c040...
Page 206: Single Address Single Transfer From Memory To I/O (16-Bit Rom)
Chapter 8 DMA Controller 8.5.2 Single Address Single Transfer from Memory to I/O (16-bit ROM) Figure 8.5.2 Single Address Single Transfer from Memory to I/O (Single Read of 32-bit Data from 16-bit ROM) 8-38...
Page 207: Single Address Single Transfer From I/O To Memory (32-Bit Sram)
Chapter 8 DMA Controller 8.5.3 Single Address Single Transfer from I/O to Memory (32-bit SRAM) SYSCLK ADDR [19:0] 1c040 00140 ACE* OE*/BUSSPRT* SWE* BWE* DATA [31:0] 00000100 ACK* DMAREQ[n] DMAACK[n] DMADONE* Figure 8.5.3 Single Address Single Transfer from I/O to Memory (Single Write of 32-bit Data to 32-bit SRAM) 8-39...
Page 208: Single Address Burst Transfer From Memory To I/O (32-Bit Rom)
Chapter 8 DMA Controller 8.5.4 Single Address Burst Transfer from Memory to I/O (32-bit ROM) Figure 8.5.4 Single Address Burst Transfer from Memory to I/O (Burst Read of 4-word Data from 32-bit ROM) 8-40...
Page 209: Single Address Burst Transfer From I/O To Memory (32-Bit Sram)
Chapter 8 DMA Controller 8.5.5 Single Address Burst Transfer from I/O to Memory (32-bit SRAM) Figure 8.5.5 Single Address Burst Transfer from I/O to Memory (Burst Write of 4-word Data from 32-bit SRAM) 8-41...
Page 210 Chapter 8 DMA Controller Figure 8.5.6 Single Address Burst Transfer from I/O to Memory (Burst Write of 8-word Data to 32-bit SRAM) 8-42...
Page 211: Single Address Single Transfer From Memory To I/O (16-Bit Rom)
Chapter 8 DMA Controller 8.5.6 Single Address Single Transfer from Memory to I/O (16-bit ROM) SYSCLK ADDR [19:0] 38080 00080 ACE* BUSSPRT* SWE* BWE* DATA [15:0] 0000 ACK* DMAREQ[n] DMAACK[n] DMADONE* Figure 8.5.7 Single Address Single Transfer from Memory to I/O (Single Read from 16-bit ROM to 16-bit Data) 8-43...
Page 212: Single Address Single Transfer From I/O To Memory (16-Bit Sram)
Chapter 8 DMA Controller 8.5.7 Single Address Single Transfer from I/O to Memory (16-bit SRAM) Figure 8.5.8 Single Address Single Transfer from I/O to Memory (Single Write of 16-bit Data to 16-bit SRAM) 8-44...
Page 213: Single Address Single Transfer From Memory To I/O (32-Bit Half Speed Rom)
Chapter 8 DMA Controller 8.5.8 Single Address Single Transfer from Memory to I/O (32-bit Half Speed ROM) Figure 8.5.9 Single Address Single Transfer from Memory to I/O (Single Read of 32-bit Data from 32-bit Half Speed ROM) 8-45...
Page 214: Single Address Single Transfer From I/O To Memory (32-Bit Half Speed Sram)
Chapter 8 DMA Controller 8.5.9 Single Address Single Transfer from I/O to Memory (32-bit Half Speed SRAM) Figure 8.5.10 Single Address Single Transfer from I/O to Memory (Single Write of 32-bit Data to 32-bit Half Speed SRAM) 8-46...
Page 215: Single Address Single Transfer From Memory To I/O (32-Bit Sram)
Chapter 8 DMA Controller 8.5.10 Single Address Single Transfer from Memory to I/O (32-bit SRAM) SDCLK ADDR [19:5] 0000 0040 RAS* CAS* CKE* DQM [3:0] DATA [31:0] ACK* DMAREQ[n] DMAACK[n] DMADONE* Figure 8.5.11 Single Address Single Transfer from Memory to I/O (Single Read of 32-bit Data from 32-bit SDRAM) 8-47...
Page 216: Single Address Single Transfer From I/O To Memory (32-Bit Sdram)
Chapter 8 DMA Controller 8.5.11 Single Address Single Transfer from I/O to Memory (32-bit SDRAM) SDCLK ADDR [19:5] 0001 0040 RAS* CAS* CKE* DQM [3:0] DATA [31:0] ACK* DMAREQ[n] DMAACK[n] DMADONE* Figure 8.5.12 Single Address Single Transfer from I/O to Memory (Single Write of 32-bit Data to 32-bit SDRAM) 8-48...
Page 217: Single Address Single Transfer From Memory To I/O Of Last Cycle When Dmadone* Signal Is Set To Output
Chapter 8 DMA Controller 8.5.12 Single Address Single Transfer from Memory to I/O of Last Cycle when DMADONE* Signal is Set to Output SDCLK ADDR [19:5] 0000 0041 RAS* CAS* CKE* OE*/BUSSPRT* DQM [7:0] DATA [63:0] ACK* DMAREQ[n] DMAACK[n] DMADONE* Figure 8.5.13 Single Address Single Transfer from Memory to I/O (Single Read of 64-bit Data from 64-bit SDRAM) 8-49...
Page 218: Single Address Single Transfer From Memory To I/O (32-Bit Sdram)
Chapter 8 DMA Controller 8.5.13 Single Address Single Transfer from Memory to I/O (32-bit SDRAM) Figure 8.5.14 Single Address Single Transfer from Memory to I/O (Single Read of 32-bit Data from 32-bit SDRAM) 8-50...
Page 219: Single Address Single Transfer From I/O To Memory (32-Bit Sdram)
Chapter 8 DMA Controller 8.5.14 Single Address Single Transfer from I/O to Memory (32-bit SDRAM) SDCLK ADDR [19:5] 0002 0080 0081 RAS* CAS* CKE* DQM [7:0] DATA [31:0] 00000100 ACK* DMAREQ[n] DMAACK[n] DMADONE* Figure 8.5.15 Single Address Single Transfer from I/O to Memory (Single Write of 32-bit Data to 32-bit SDRAM) 8-51...
Page 220: External I/O Device - Sram Dual Address Transfer
Chapter 8 DMA Controller 8.5.15 External I/O Device – SRAM Dual Address Transfer SYSCLK CE* (SRAM) CE* (I/O device) ADDR [19:0] ACE* BUSSPRT* SWE* BWE* DATA [31:0] Valid Valid Valid Valid Valid Valid Valid Valid ACK* DMAREQ[n] DMAACK[n] DMADONE* Figure 8.5.16 Dual Address Transfer from External I/O Device to SRAM (8-word Burst Transfer to 32-bit Bus SRAM) 8-52...
Page 221 Chapter 8 DMA Controller SYSCLK CE* (SRAM) CE* (I/O device) ADDR [19:0] ACE* BUSSPRT* SWE* BWE* DATA [31:0] Valid Valid Valid Valid ACK* DMAREQ[n] DMAACK[n] DMADONE* Figure 8.5.17 Dual Address Transfer from SRAM to External I/O Device (4-word Burst Transfer from 32-bit Bus SRAM) 8-53...
Page 222: External I/O Device - Sdram Dual Address Transfer
Chapter 8 DMA Controller 8.5.16 External I/O Device – SDRAM Dual Address Transfer SDCLK/SYSCLK ADDR [19:0] RAS* CAS* BUSSPRT* DQM[7:0] DATA [31:0] Valid ACK* ACE* SWE* BWE* DMAREQ[n] DMAACK[n] DMADONE* Figure 8.5.18 Dual Address Transfer from External I/O Device to SDRAM (4-word Burst Transfer to 32-bit SDRAM) 8-54...
Page 223 Chapter 8 DMA Controller SDCLK/SYSCLK ADDR [19:0] RAS* CAS* OE*/BUSSPRT* DQM[7:0] DATA [31:0] Valid Valid Valid Valid Valid Valid Valid Valid ACK* ACE* SWE* BWE* DMAREQ[n] DMAACK[n] DMADONE* Figure 8.5.19 Dual Address Transfer from SDRAM to External I/O Device (8-word Burst Transfer from 32-bit SDRAM) 8-55...
Page 224: External I/O Device (Non-Burst) - Sdram Dual Address Transfer
Chapter 8 DMA Controller 8.5.17 External I/O Device (Non-burst) – SDRAM Dual Address Transfer SDCLK/SYSCLK ADDR[19:0] RAS* CAS* BUSSPRT* DQM[7:0] DATA[31:0] Valid V V V ACK* ACE* SWE* BWE* DMAREQ[n] DMAACK[n] DMADONE* Figure 8.5.20 Dual Address Transfer from External I/O Device (Non-Burst) to SDRAM (4-word Burst Transfer to 32-bit SDRAM: Set DMCCRn.SBINH to “1”) 8-56...
Page 225 Chapter 8 DMA Controller SDCLK/SYSCLK ADDR[19:0] RAS* CAS* OE*/BUSSPRT* DQM[7:0] DATA[31:0] V V V V Valid Valid Valid Valid ACK* ACE* BWE* DMAREQ[n] DMAACK[n] DMADONE* Figure 8.5.21 Dual Address Transfer from SDRAM to External I/O Device (4-word Burst Transfer from 32-bit SDRAM: Set DMCCRn.DBINH to “1”) 8-57...
Page 226 Chapter 8 DMA Controller 8-58...
Page 227: Sdram Controller
Chapter 9 SDRAM Controller SDRAM Controller Characteristics The SDRAM Controller (SDRAMC) generates the control signals required to interface with the SDRAM. There are a total of four channels, which can each be operated independently. The SDRAM Controller supports various bus configurations and a memory size of up to 2 GB. The SDRAM has the following characteristics.
Page 228: Block Diagram
Chapter 9 SDRAM Controller Block Diagram SDRAMC SDCS [3:0]* Channel 0 – 3 Control G-Bus Control Register Circuit Interface G-Bus Control I/F Signal RAS* Timing Register CAS* DQM [3:0] Command/Load Register Refresh Counter EBIF Control Signal ADDR [19:16], SADDR10, ADDR[14:5] G-Bus I/FSignal DATA [31:0]...
Page 229: Detailed Explanation
Chapter 9 SDRAM Controller Detailed Explanation 9.3.1 Supported SDRAM Configurations This controller supports the SDRAM Configurations listed below in Table 9.3.1. The MW field of the SDRAM Channel Control Register (SDCCRn) can be used to separately set the data bus width for each channel to either 32 bits or 16 bits. DATA[15:0] and DQM[1:0] are used when using a 16-bit data bus.
Page 230: Address Mapping
Chapter 9 SDRAM Controller 9.3.2 Address Mapping 9.3.2.1 Physical Address Mapping It is possible to map each of the four channels to an arbitrary physical address using the Base Address field (SDCCRn.BA[31:21]) of the SDRAM Channel Control Register and the Address Mask Field (SDCCRn.AM[31:21]).
Page 231 Chapter 9 SDRAM Controller 9.3.2.2 Address Signal Mapping (32-bit Data Bus) Table 9.3.2 shows the address signal mapping when using a 32-bit data bus. B0 is used in the bank selection in memory with a two-bank configuration. [B1:B0] are used in the bank selection in memory with a four-bank configuration.
Page 232 Chapter 9 SDRAM Controller Table 9.3.2 Address Signal Mapping (32-bit Data Bus) (2/2) Row Address Width = 12 Column Address Width = 11 Address Bit ADDR [19:5] DR10 (B0) (B1) (AP) Column Address Row Address Row Address Width = 13 Column Address Width = 8 Address Bit ADDR [19:5]...
Page 233 Chapter 9 SDRAM Controller 9.3.2.3 Address Signal Mapping (16-bit Data Bus) Table 9.3.3 shows the address signal mapping when using a 16-bit data bus. B0 is used in the bank selection in memory with a two-bank configuration. [B1:B0] are used in the bank selection in memory with a four-bank configuration.
Page 234 Chapter 9 SDRAM Controller Table 9.3.3 Address Signal Mapping (16-bit Data Bus) (2/2) Row Address Width = 12 Column Address Width = 11 Address Bit ADDR [19:5] DR10 (B0) (B1) (AP) Column Address Row Address Row Address Width = 13 Column Address Width = 8 Address Bit ADDR [19:5]...
Page 235: Initialization Of Sdram
Chapter 9 SDRAM Controller 9.3.3 Initialization of SDRAM The TX4925 Command Register has functions for generating the cycles required for initializing SDRAM and SyncFlash. Using software to set each register makes it possible to execute initial settings at a particular timing. (1) Set the SDRAM Channel Control Register (SDCCRn).
Page 236: Low Power Consumption Function
Chapter 9 SDRAM Controller 9.3.4 Low Power Consumption Function 9.3.4.1 Power Down Mode, Self-Refresh Mode, Deep Power Down Mode SDRAM has two low power consumption modes called the Power Down mode and the Self- Refresh mode. Memory data is lost in the case of the Power Down mode since Memory Refresh is not performed, but the amount of power consumed is reduced the most.
Page 237: Bus Errors
Chapter 9 SDRAM Controller 9.3.4.2 Advanced CKE Advanced CKE is a function that speeds up the CKE assertion and deassertion timing by 1 clock cycle. This function is set using the Address CKE bit (SDCTR.ACE) of the SDRAM Timing Register. Advanced CKE assumes that it will be used in a system where SDRAM data is saved even when the power to the TX4925 itself is cut.
Page 238: Clock Feedback
Chapter 9 SDRAM Controller 9.3.8 Clock Feedback When performing Read access at fast rates like 80 MHz, there may be insufficient set up time if an attempt to directly latch Read data with the internal clock is made. With the TX4925, it is possible to latch data using SDRAM clock SDCLKIN that is input from outside the chip.
Page 239: Sdram Channel Control Register (Sdccr0) 0X8000 (Ch. 0) (Sdccr1) 0X8004 (Ch. 1) (Sdccr2) 0X8008 (Ch. 2) (Sdccr3) 0X800C (Ch. 3)
Chapter 9 SDRAM Controller 9.4.1 SDRAM Channel Control Register (SDCCR0) 0x8000 (ch. 0) (SDCCR1) 0x8004 (ch. 1) (SDCCR2) 0x8008 (ch. 2) (SDCCR3) 0x800C (ch. 3) AM[31:27] : Type : Initial 0x000 value AM[26:21] Reserved R/W : Type : Initial 0x00 value Bits Mnemonic...
Page 240 Chapter 9 SDRAM Controller Bits Mnemonic Field Name Description Column Size Column Size (Initial value: 000, R/W) Specifies the column size. 000: 256 words (8 bits) 001: 512 words (9 bits) 010: 1024 words (10 bits) 011: 2048 words (11 bits) 100: 4096 words (12 bits) 101 –...
Page 241: Sdram Timing Register (Sdctr) 0X8020
Chapter 9 SDRAM Controller 9.4.2 SDRAM Timing Register (SDCTR) 0x8020 PDAE CASL R/W : Type : Initial 00000 value : Type : Initial 0x270 value Bits Mnemonic Field Name Description 31:29 Bank Cycle Time Bank Cycle Time (t ) (Initial value: 101, R/W) ( * 2) Specifies the bank cycle time.
Page 242 Chapter 9 SDRAM Controller Bits Mnemonic Field Name Description 22:18 Refresh Counter Refresh Counter (Initial value: 00000, R/W) This counter is decremented at each refresh. If the refresh circuit is activated and a value other than “0” is loaded, this field becomes a down counter that stops at “0”. A value other than “0”...
Page 243: Sdram Command Register (Sdccmd) 0X802C
Chapter 9 SDRAM Controller 9.4.3 SDRAM Command Register (SDCCMD) 0x802C MDLNO VERNO : Type : Initial 0x21 0x10 value Reserved : Type : Initial value Bits Mnemonic Field Name Description 31:24 MDLNO Model Number Model Number (Initial value: 0x21, R) Indicates the model number.
Page 244: Timing Diagrams
Chapter 9 SDRAM Controller Timing Diagrams Please note the following when referring to the timing diagrams in this section: the shaded area each diagram expresses values that have yet to be determined. 9.5.1 Single Read (32-bit Bus) SDCLK SDCS* ADDR [19:16] SADDR10 7fff 0000...
Page 245 Chapter 9 SDRAM Controller SDCLK SDCS* ADDR [19:16] SADDR10 7fff 0000 ADDR[14:5] RAS* CAS* DQM [3:0] DATA [31:0] ACK*/READY* = 3, t = 3, t = 1, 32-bit Bus) Figure 9.5.2 Single Read (t CASL 9-19...
Page 246: Single Write (32-Bit Bus)
Chapter 9 SDRAM Controller 9.5.2 Single Write (32-bit Bus) SDCLK SDCS* ADDR [19:16] SADDR10 0000 0400 ADDR[14:5] RAS* CAS* DQM [3:0] DATA [31:0] ACK*/READY* = 2, t = 0, 32-bit Bus) Figure 9.5.3 One-Word Single Write (t 9-20...
Page 247 Chapter 9 SDRAM Controller SDCLK SDCS* ADDR [19:16] SADDR10 0000 0400 ADDR[14:5] RAS* CAS* DQM [3:0] DATA [31:0] ACK*/READY* = 3, t = 1, 32-bit Bus) Figure 9.5.4 One-Word Single Write (t 9-21...
Page 248: Burst Read (32-Bit Bus)
Chapter 9 SDRAM Controller 9.5.3 Burst Read (32-bit Bus) SDCLK SDCS* ADDR [19:16] SADDR10 0001 0000 0005 0002 0004 0007 ADDR[14:5] RAS* CAS* DQM [3:0] DATA [31:0] ACK*/READY* = 2, t = 2, t = 0, 32-bit Bus) Figure 9.5.5 Four-Word Burst Read (t CASL 9-22...
Page 249: Burst Write (32-Bit Bus)
Chapter 9 SDRAM Controller 9.5.4 Burst Write (32-bit Bus) SDCLK SDCS* ADDR [19:16] SADDR10 0000 0000 0402 ADDR[14:5] RAS* CAS* DQM [3:0] DATA [31:0] ACK*/READY* = 2, t = 0, 32-bit Bus) Figure 9.5.6 Four-Word Burst Write (t 9-23...
Page 250: Burst Write (32-Bit Bus, Slow Write Burst)
Chapter 9 SDRAM Controller 9.5.5 Burst Write (32-bit Bus, Slow Write Burst) = 2, t = 0, 32-bit Bus, Slow Write Burst) Figure 9.5.7 Four-Word Burst Write (t 9-24...
Page 251: Single Read (16-Bit Bus)
Chapter 9 SDRAM Controller 9.5.6 Single Read (16-bit Bus) SDCLK SDCS* ADDR [19:16] SADDR10 7fff 0000 ADDR[14:5] RAS* CAS* DQM [3:0] DATA [15:0] ACK*/READY* = 2, t = 2, t = 0, 16-bit Bus) Figure 9.5.8 One Word Single Read (t CASL 9-25...
Page 252 Chapter 9 SDRAM Controller SDCLK SDCS* ADDR [19:16] SADDR10 7fff 0000 ADDR[14:5] RAS* CAS* DQM [3:0] DATA [15:0] ACK*/READY* = 2, t = 3, t = 0, 16-bit Bus) Figure 9.5.9 Half-Word Single Read (t CASL 9-26...
Page 253: Single Write (16-Bit Bus)
Chapter 9 SDRAM Controller 9.5.7 Single Write (16-bit Bus) SDCLK SDCS* ADDR [19:16] SADDR10 0000 0400 ADDR[14:5] RAS* CAS* DQM [3:0] DATA [15:0] ACK*/READY* = 2, t = 0, 16-bit Bus) Figure 9.5.10 One-Word Single Write (t 9-27...
Page 254 Chapter 9 SDRAM Controller SDCLK SDCS* ADDR [19:16] SADDR10 0000 0400 ADDR[14:5] RAS* CAS* DQM [3:0] DATA [15:0] ACK*/READY* = 3, t = 0, 16-bit Bus) Figure 9.5.11 Half-Word Single Write (t 9-28...
Page 255: Low Power Consumption And Power Down Mode
Chapter 9 SDRAM Controller 9.5.8 Low Power Consumption and Power Down Mode SDCLK SDCS* ADDR [19:16] SADDR10 ADDR[14:5] RAS* CAS* DQM [3:0] DATA [31:0] ACK*/READY* Figure 9.5.12 Transition to Low Power Consumption Mode (SDCTR.ACE = 0) 9-29...
Page 256 Chapter 9 SDRAM Controller SDCLK SDCS* ADDR [19:16] SADDR10 ADDR[14:5] RAS* CAS* DQM [3:0] DATA [31:0] ACK*/READY* Figure 9.5.13 Transition to Power Down Mode 9-30...
Page 257 Chapter 9 SDRAM Controller Figure 9.5.14 Return From Low Power Consumption/Power Down Mode (SDCTR.PDAE=0, SDCTR.ACE=0) 9-31...
Page 258 Chapter 9 SDRAM Controller SDCLK SDCS* ADDR [19:16] SADDR10 0000 0400 ADDR[14:5] RAS* CAS* DQM [3:0] DATA [31:0] ACK*/READY* Figure 9.5.15 Power Down Auto Entry (SDCTR.PDAE=1, SDCTR.ACE=0) 9-32...
Page 259: Sdram Usage Example
Chapter 9 SDRAM Controller SDRAM Usage Example Figure 9.6.1 illustrates an example SDRAM connection. TX4925 SDRAM (×16 bits) DQM [3] DQM [2] DQM [1] DQM [0] DQM [3:0] ADDR [17:16] UDQM LDQM UDQM LDQM SADDR10 ADDR [19:16] ADDR[14:5] SADDR10 A [12:0] A [12:0] ADDR [19] ADDR[14:5]...
Page 260 Chapter 9 SDRAM Controller 9-34...
Page 261: Pci Controller
Chapter 10 PCI Controller 10. PCI Controller 10.1 Features The TX4925 PCI Controller functions as a bus bridge between the TX4925 External PCI and the internal bus (G-Bus). 10.1.1 Overall • Compliant to “PCI Local Bus Specification Revision 2.2” • PCI Bus: 32-bit data bus;...
Page 262: Pci Arbiter
Chapter 10 PCI Controller 10.1.4 PCI Arbiter • Supports four external PCI bus masters • Uses the Programmable Fairness algorithm (two levels with different priorities for four round- robin request/grant pairs) • Supports bus parking • Bus master uses the Most Recently Used algorithm •...
Page 263: Block Diagram
Chapter 10 PCI Controller 10.2 Block Diagram TX49/H2 Core Memory Controller DMA Controller Arbiter G-Bus PCI Controller Retry G-Bus I/F Targ. cont. Mast. cont. PDMAC (32-bit × 16) (PCI→G-Bus) (G-Bus→PCI) 32-bits × 16 32-bits × 32 x 3 ch 32-bits × 8 Config EBUSC Arb.
Page 264: Detailed Explanation
Chapter 10 PCI Controller 10.3 Detailed Explanation 10.3.1 Terminology Explanation The following terms are used in this chapter. • Initiator Means the bus Master of the PCI Bus. The TX4925 operates as the initiator when it obtains the PCI Bus and issues PCI access. •...
Page 265 Chapter 10 PCI Controller Registers in the PCI Controller Control Register that include an offset address in the range from 0xD000 to 0xD07F can only be accessed when in the Host mode and cannot be accessed when in the Satellite mode. These registers correspond to PCI Configuration Space Registers that an external PCI Host device accesses when in the Satellite mode.
Page 266: Supported Pci Bus Commands
Chapter 10 PCI Controller 10.3.3 Supported PCI Bus Commands Table 10.3.1 shows the PCI Bus commands that the PCI Controller supports. Table 10.3.1 Supported PCI Bus Commands C/BE Value PCI Command As Initiator As Target ⎯ 0000 Interrupt Acknowledge † ⎯...
Page 267 Chapter 10 PCI Controller The Memory Read command is issued if these conditions are not met, namely, if “0” is set to the Cache Line Size field (PCICFG1.CLS) of the PCI Configuration 1 Register. In the case of the target, a normal G-Bus cycle is issued to the address mapped from the PCI Bus to the G-Bus. •...
Page 268: Initiator Access (G-Bus → Pci Bus Address Conversion)
Chapter 10 PCI Controller • Special Cycle This command issues specially cycles as the initiator only when in the Host mode. This command issues special cycles on the PCI Bus when writing to the G2P Special Cycle Data Register (G2PSPC). The written value is output as the special cycle data. The TX4925 does not support special cycles as the target.
Page 269 Chapter 10 PCI Controller When expressed as a formula, conversion of a G-Bus address (GBusAddr[31:0]) into a PCI Bus Address (PCIAddr[31:0]) is as follows below. GBASE[31:8], PBASE[31:8], and AM[28:8] each represent the setting register of the corresponding access window indicated below in Table 10.3.2. The “&”...
Page 270: Target Access (Pci Bus → G-Bus Address Conversion)
Chapter 10 PCI Controller Table 10.3.3 Initiator Access Space Properties Register Enable Word Swap Memory Space 0 BusMasterEnable & G2PCFG.G2PM0EN G2PCFG.BSWAPM0 Memory Space 1 BusMasterEnable & G2PCFG.G2PM1EN G2PCFG.BSWAPM1 Memory Space 2 BusMasterEnable & G2PCFG.G2PM2EN G2PCFG.BSWAPM2 I/O Space BusMasterEnable & G2PCFG.G2PIOEN G2PCFG.BSWAPIO BusMasterEnable: Host mode:...
Page 271 Chapter 10 PCI Controller When expressed as a formula, conversion of a PCI Bus Address (PCIAddr[31:0]) into a G-Bus address (GBusAddr[31:0]) is as follows below. GBASE[31:8], PBASE[31:8], and AM[28:20]/AM[15:8] each represent the setting register of the corresponding access window indicated below in Table 10.3.4.
Page 272 Chapter 10 PCI Controller Figure 10.3.6 and Figure 10.3.7 illustrate this address conversion. PCIAddr Compare 0x00000 PBASE 0 0 - - - 0 1 1 - - - 1 0x00000 0x00000 GBASE GBusAddr Figure 10.3.6 Memory Address Conversion for Target (PCI Bus → G-Bus Address Conversion) PCIAddr Compare PBASE...
Page 273: Post Write Function
Chapter 10 PCI Controller It is possible to set each space to valid/invalid, pre-fetch Read to valid/invalid, or to perform Word Swap (see 10.3.7). Table 10.3.5 shows the settings registers for these properties. When pre-fetch Reads are set to valid, data transfer is performed on the G-Bus according to the size set by the Target Pre-fetch Read Burst Length Field (P2GMnCTR.TPRBL) of the P2G Memory Space n Control Register during a PCI target Read transaction.
Page 274: Power Management
Chapter 10 PCI Controller Initial state operation matches the correspondence between the address and byte data regardless of the endian mode (operation is address consistent). For example, if WORD (16-bit) data is written to address 0 of the PCI Bus when the TX4925 is in the Big Endian mode, the upper byte (address 0 in Big Endian) is written to PCI Bus address 0 and the lower byte (address 1 in Big Endian) is written to address 1 of the PCI Bus.
Page 275: Pdmac (Pci Dma Controller)
Chapter 10 PCI Controller Power On Reset (RESET* Uninitialized RST* Initialization by the (RESET System Software cold D0 Active Software Reset VCC Cut-off Change PMCSR PowerState Figure 10.3.8 Transition of the Power Management States 10.3.9 PDMAC (PCI DMA Controller) The PCI DMA Controller (PDMAC) is a one-channel PCI Director Memory Access (DMA) controller.
Page 276 Chapter 10 PCI Controller (6) Termination Report When the DMA data transfer terminates normally, the Normal Data Transfer Complete bit (NTCMP) of the PDMAC Status Register (PDMSTATUS) is set. An interrupt is then reported if the Normal Data Transfer Complete Interrupt Enable bit (NTCMPIE) of the PDMAC Configuration Register is set.
Page 277 Chapter 10 PCI Controller (5) DMA Transfer Initiation Setting the address of the DMA Command descriptor that is at the beginning of the Chain List in the PDMAC Chain Address Register (PDMCA) automatically initiates DMA transfer. First, the values stored in each field of the DMA Command Descriptor that is at the beginning of the Chain List are read to each corresponding PDMAC Register, then DMA transfer is performed according to the read values.
Page 278 Chapter 10 PCI Controller (3) Chain Enable bit checking Reads the value of the Chain Enable bit (CHNEN) in the PDMAC Configuration Register (PDMCFG). If the read value is “0”, then the Chain Address field value of the DMA Command Descriptor indicated by the address stored in the PDMAC Chain Address Register (PDMCA) is written to the PDMAC Chain Address Register (PDMCA).
Page 279: Error Detection, Interrupt Reporting
Chapter 10 PCI Controller 10.3.10 Error Detection, Interrupt Reporting The PCI Controller reports the four following types of interrupts to the Interrupt Controller (IRC). • Normal Operation Interrupt (Interrupt Number: 20, PCIC) • PDMAC Interrupt (Interrupt Number: 19, PDMAC) • Power Management Interrupt (Interrupt Number: 30, PCIPME) •...
Page 280: Pci Bus Arbiter
Chapter 10 PCI Controller 10.3.10.4 Error Detection Interrupts Name Status Bit Interrupt Enable Bit Bus Error Detection DPEIE PCISTATUS PCIMASK System Error Signal SSEIE PCISSTATUS Master Data Parity Error MDPE MDPEIE Master Direct Fatal Error MDFE MDFEIE Master Direct Parity Error MPRE MPREIE G2PSTATUS...
Page 281 Chapter 10 PCI Controller 10.3.11.2 Priority Control As illustrated below in Figure 10.3.9, a combination of two round-robin sequences is used as the arbitration algorithm that determines the priority of Internal PCI Bus arbiter bus requests. The round-robin with the lower priority (Level 2) consists of Masters W - Z, and the round-robin with the high priority (Level 1), consists of Master A - D and Level 2 Masters.
Page 282: Pci Boot
Chapter 10 PCI Controller 10.3.11.3 Bus Parking The On-chip PCI Bus Arbiter supports bus parking. The last PCI Bus Master is made the Park Master when the Fix Park Master bit (FIXPM) of the PCI Bus Arbiter Configuration Register (PBACFG) is cleared (in the default state). When this bit is set, the Internal PCI Bus Arbiter Request A Port (Master A) becomes the Park Master.
Page 283: Set Configuration Space
Chapter 10 PCI Controller 10.3.13 Set Configuration Space In Table 10.5.1, the values for the registers inside the PCI Configuration Space Register that have a gray background can be rewritten using one of the following method. 10.3.13.1 Set the Configuration Space Using Software Reset By using the following procedure, it is possible to use the software to set the configuration space.
Page 284: Pci Controller Control Register
Chapter 10 PCI Controller 10.4 PCI Controller Control Register Table 10.4.1 lists the registers contained in the PCI Controller Control Register. Parentheses in the register names indicate the corresponding PCI Configuration Space Register. Table 10.4.1 PCI Controller Control Register (1/2) Section Address Bit Width...
Page 285 Chapter 10 PCI Controller Table 10.4.1 PCI Controller Control Register (2/2) Section Address Bit Width Mnemonic Register Name 10.4.39 0xD158 G2PM1PBASE G2P Memory Space 1 PCI Base Address Register 10.4.40 0xD160 G2PM2PBASE G2P Memory Space 2 PCI Base Address Register 10.4.41 0xD168 G2PIOPBASE...
Page 286: Id Register (Pciid) 0Xd000
Chapter 10 PCI Controller 10.4.1 ID Register (PCIID) 0xD000 The Device ID field corresponds to the Device ID Register in the PCI Configuration Space, and the Vendor ID field corresponds to the Vendor ID register of the PCI Configuration Space. These two fields can be modified by software only when PCICCFG.ConfigBusy=1 after Reset.
Page 287: Pci Status, Command Register (Pcistatus) 0Xd004
Chapter 10 PCI Controller 10.4.2 PCI Status, Command Register (PCISTATUS) 0xD004 The upper 16 bits correspond to the Status Register in the PCI Configuration Space, and the lower 16 bits correspond to the Command Register in the PCI Configuration Space. This register cannot be accessed when in the Satellite mode.
Page 288 Chapter 10 PCI Controller Bits Mnemonic Field Name Explanation MDPE Master Data Master Data Parity Error (Initial value: 0, R/W1C) Parity Error Indicates the a parity error occurred when the PCI Controller is the PCI initiator. This bit is not set when the PCI Controller is the target. This bit is set when all of the three following conditions are met.
Page 289: Class Code, Revision Id Register (Pciccrev) 0Xd008
Chapter 10 PCI Controller 10.4.3 Class Code, Revision ID Register (PCICCREV) 0xD008 The Class Code field corresponds to the Class Code Register of the PCI Configuration Space, and the Revision ID field corresponds to the Revision ID Register of the PCI Configuration Space. These two fields can be modified by software only when PCICCFG.ConfigBusy=1 after Reset.
Page 290: Pci Configuration 1 Register (Pcicfg1) 0Xd00C
Chapter 10 PCI Controller 10.4.4 PCI Configuration 1 Register (PCICFG1) 0xD00C The following fields correspond to the following registers. BIST field → BIST Register of the PCI Configuration Space Header Type field → Header Type Register in the PCI Configuration Space Latency Timer field →...
Page 291: P2G Memory Space 0 Pci Base Address Register (P2Gm0Pbase) 0Xd010
Chapter 10 PCI Controller 10.4.5 P2G Memory Space 0 PCI Base Address Register (P2GM0PBASE) 0xD010 This register corresponds to the Memory Space 0 Base Address Register at offset address 0x10 of the PCI Configuration Space. This register cannot be accessed when the PCI Controller is in the Satellite mode. BA[31:20] Reserved : Type...
Page 292: P2G Memory Space 1 Pci Base Address Register (P2Gm1Pbase) 0Xd014
Chapter 10 PCI Controller 10.4.6 P2G Memory Space 1 PCI Base Address Register (P2GM1PBASE) 0xD014 This register corresponds to the Memory Space 1 Base Address Register at offset address 0x14 of the PCI Configuration Space. This register cannot be accessed when the PCI Controller is in the Satellite mode. BA[31:20] Reserved : Type...
Page 293: P2G Memory Space 2 Pci Base Address Register (P2Gm2Pbase) 0Xd018
Chapter 10 PCI Controller 10.4.7 P2G Memory Space 2 PCI Base Address Register (P2GM2PBASE) 0xD018 This register corresponds to the Memory Space 2 Base Address Register at offset address 0x18 of the PCI Configuration Space. This register cannot be accessed when the PCI Controller is in the Satellite mode. BA[31:20] Reserved : Type...
Page 294: P2G I/O Space Pci Base Address Register (P2Giopbase) 0Xd01C
Chapter 10 PCI Controller 10.4.8 P2G I/O Space PCI Base Address Register (P2GIOPBASE) 0xD01C This register corresponds to the I/O Space Base Address at offset address 0x1C of the PCI Configuration Space. This register cannot be accessed when the PCI Controller is in the Satellite mode. BA[31:16] : Type 0x0000...
Page 295: Subsystem Id Register (Pcisid) 0Xd02C
Chapter 10 PCI Controller 10.4.9 Subsystem ID Register (PCISID) 0xD02C The Subsystem ID field corresponds to the Subsystem ID Register of the PCI Configuration Space, and the Subsystem Vendor ID field corresponds to the Subsystem Vendor ID Register of the PCI Configuration Space.
Page 296: Capabilities Pointer Register (Pcicapptr) 0Xd034
Chapter 10 PCI Controller 10.4.10 Capabilities Pointer Register (PCICAPPTR) 0xD034 The Capabilities Pointer field corresponds to the Capabilities Pointer Register of the PCI Configuration Space. This register cannot be accessed when the PCI Controller is in the Satellite mode. Reserved : Type : Initial value Reserved...
Page 297: Pci Configuration 2 Register (Pcicfg2) 0Xd03C
Chapter 10 PCI Controller 10.4.11 PCI Configuration 2 Register (PCICFG2) 0xD03C The following fields correspond to the following registers: Max. Latency field → Max_Lat Register of the PCI Configuration Space Min. Grant field → Min_Gnt Register of the PCI Configuration Space Interrupt Pin field →...
Page 298: G2P Timeout Count Register (G2Ptocnt) 0Xd040
Chapter 10 PCI Controller 10.4.12 G2P Timeout Count Register (G2PTOCNT) 0xD040 The Retry Timeout field corresponds to the Retry Timeout Value Register of the PCI Configuration Space, and the TRDY Timeout field corresponds to the TRDY Timeout Value Register of the PCI Configuration Space.
Page 299: G2P Configuration Register (G2Pcfg) 0Xd060
Chapter 10 PCI Controller 10.4.13 G2P Configuration Register (G2PCFG) 0xD060 Reserved : Type : Initial value Reserved IRBER ASERR Reserved BSWAPI BSWAPM0 BSWAPM1 BSWAPM2 BSWAPIO G2PM0EN G2PM1EN G2PM2EN G2PIOEN R/W R/W1C : Type : Initial value Bits Mnemonic Field Name Description ⎯...
Page 300 Chapter 10 PCI Controller Bits Mnemonic Field Name Description G2PM2EN Initiator Memory Initiator Memory Space 2 Enable (Initial value: Normal Mode: 0; PCI Boot Mode: 1, Space 2 Enable R/W) Controls PCI initiator access to Memory Space 2. 1: Memory Space 2 is valid. 0: Memory Space 2 is invalid.
Page 301: G2P Status Register (G2Pstatus) 0Xd064
Chapter 10 PCI Controller 10.4.14 G2P Status Register (G2PSTATUS) 0xD064 Reserved : Type : Initial value Reserved IOBFE IIBFE MDFE MDPE Reserved IDTTOE IDRTOE R/W1C R/W1C R/W1C R/W1C : Type : Initial value Bits Mnemonic Field Name Description ⎯ ⎯ 31:9 Reserved Initiator Out-...
Page 302: G2P Interrupt Mask Register (G2Pmask) 0Xd068
Chapter 10 PCI Controller 10.4.15 G2P Interrupt Mask Register (G2PMASK) 0xD068 Reserved : Type : Initial value Reserved Reserved MDFEIE MDPEIE IDTTOEIE IDRTOEIE R/W : Type : Initial value Bits Mnemonic Field Name Description ⎯ ⎯ 31:7 Reserved Master Direct MDFEIE Master Direct Fatal Error Interrupt Enable (Initial value: 0, R/W) Fatal Error...
Page 303: Satellite Mode Pci Status Register (Pcisstatus) 0Xd088
Chapter 10 PCI Controller 10.4.16 Satellite Mode PCI Status Register (PCISSTATUS) 0xD088 The PCI Status, Command Register (PCISTATUS) or the PMCSR Register of the Configuration Space cannot be accessed when the PCI Controller is in the Satellite mode. It is possible however to read values from either of these registers.
Page 304: Pci Status Interrupt Mask Register (Pcimask) 0Xd08C
Chapter 10 PCI Controller 10.4.17 PCI Status Interrupt Mask Register (PCIMASK) 0xD08C Reserved : Type : Initial value DPEIE SSEIE RMAIE RTAIE STAIE Reserved Reserved MDPEIE : Type : Initial value Bits Mnemonic Field Name Description ⎯ ⎯ 31:16 Reserved Detected Parity DPEIE Detected Parity Error Interrupt Enable (Initial value: 0, R/W)
Page 305: P2G Configuration Register (P2Gcfg) 0Xd090
Chapter 10 PCI Controller 10.4.18 P2G Configuration Register (P2GCFG) 0xD090 Reserved : Type : Initial value Reserved FTRD FTA TOBFR TIBFR Reserved R/W : Type : Initial value Bits Mnemonic Field Name Description ⎯ ⎯ 31:5 Reserved ⎯ Reserved Don’t write one in this bit (Initial value: 0, R/W). FTRD Force Target Force Target Retry/Disconnect (Initial value: 0, R/W)
Page 306: P2G Status Register (P2Gstatus) 0Xd094
Chapter 10 PCI Controller 10.4.19 P2G Status Register (P2GSTATUS) 0xD094 Reserved : Type : Initial value Reserved TOBFE TIBFE PMSC PERR R/W1C R/W1C R/W1C : Type : Initial value Bits Mnemonic Field Name Description ⎯ ⎯ 31:5 Reserved TOBFE Target Out-Bound Target Out-Bound FIFO Empty (Initial value: 1, R) FIFO Empty 1: Indicates that the Target Out-Bound FIFO is empty.
Page 307: P2G Interrupt Mask Register (P2Gmask) 0Xd098
Chapter 10 PCI Controller 10.4.20 P2G Interrupt Mask Register (P2GMASK) 0xD098 Reserved : Type : Initial value Reserved GBEIE PMSCIE PERRIE R/W : Type : Initial value Bits Mnemonic Field Name Description ⎯ ⎯ 31:3 Reserved PMSCIE Power Power Management State Change Interrupt Enable (Initial value: 0, R/W) Management Generates an interrupt when the PowerState field of the Power Management Register State Change...
Page 308: P2G Current Command Register (P2Gccmd) 0Xd09C
Chapter 10 PCI Controller 10.4.21 P2G Current Command Register (P2GCCMD) 0xD09C Reserved : Type : Initial value Reserved TCCMD : Type : Initial value Bits Mnemonic Field Name Description ⎯ ⎯ 31:4 Reserved TCCMD Target Current Target Current Command (Initial value: 0x0, R) Command Indicates the PCI command within the target access process that is currently in Register...
Page 309: Pci Bus Arbiter Request Port Register (Pbareqport) 0Xd100
Chapter 10 PCI Controller 10.4.22 PCI Bus Arbiter Request Port Register (PBAREQPORT) 0xD100 This register sets the correlation between each PCI Bus request source (PCI Controller and REQ[3:0]) and each Internal PCI Bus Arbiter Request port (Master A - D, W - Z) (see Figure 10.3.9). When changing these settings, each of the eight field values must always be set to different values.
Page 310 Chapter 10 PCI Controller Bits Mnemonic Field Name Description 18:16 ReqDP Request D Port Request D Port (Initial value: 100, R/W) Sets the PCI Bus Master that connects to the Internal PCI Bus Arbiter Request D Port (Master D). 111: Makes the PCI Controller Master D. 110: Reserved 101: Reserved 100: Reserved...
Page 311: Pci Bus Arbiter Configuration Register (Pbacfg) 0Xd104
Chapter 10 PCI Controller 10.4.23 PCI Bus Arbiter Configuration Register (PBACFG) 0xD104 This register is only valid when using the on-chip PCI Bus Arbiter. Reserved : Type : Initial value Reserved FIXPA RPBA PBAEN BMCEN : Type : Initial value Bits Mnemonic Field Name...
Page 312: Pci Bus Arbiter Status Register (Pbastatus) 0Xd108
Chapter 10 PCI Controller 10.4.24 PCI Bus Arbiter Status Register (PBASTATUS) 0xD108 This register is only valid when using the on-chip PCI Bus Arbiter. Reserved : Type : Initial value Reserved R/W1C : Type : Initial value Bits Mnemonic Field Name Description ⎯...
Page 313: Pci Bus Arbiter Interrupt Mask Register (Pbamask) 0Xd10C
Chapter 10 PCI Controller 10.4.25 PCI Bus Arbiter Interrupt Mask Register (PBAMASK) 0xD10C This register is only valid when using the on-chip PCI Bus Arbiter. Reserved : Type : Initial value Reserved BMIE R/W : Type : Initial value Bits Mnemonic Field Name Description...
Page 314: Pci Bus Arbiter Broken Master Register (Pbabm) 0Xd110
Chapter 10 PCI Controller 10.4.26 PCI Bus Arbiter Broken Master Register (PBABM) 0xD110 This register indicates the acknowledged Broken Master. This register sets the bit that corresponds to the PCI Master device that was acknowledged as the Broken Master when the Broken Master Check Enable bit (BMCEN) in the PCI Bus Arbiter Configuration Register (PBACFG) is set.
Page 315 Chapter 10 PCI Controller Bits Mnemonic Field Name Description BM_Y Broken Master Broken Master Y (Initial value: 0, R/W) Indicates whether PCI Bus Master Y is a Broken Master. 1: PCI Bus Master Y was acknowledged as a Broken Master. 0: PCI Bus Master Y was not acknowledged as a Broken Master.
Page 316: Pci Bus Arbiter Current Request Register (Pbacreq) 0Xd114
Chapter 10 PCI Controller 10.4.27 PCI Bus Arbiter Current Request Register (PBACREQ) 0xD114 This register is a diagnostic register that is only valid when using the on-chip PCI Bus Arbiter. Reserved : Type : Initial value Reserved CPCIBRS : Type 0x00 : Initial value Bits...
Page 317: Pci Bus Arbiter Current Grant Register (Pbacgnt) 0Xd118
Chapter 10 PCI Controller 10.4.28 PCI Bus Arbiter Current Grant Register (PBACGNT) 0xD118 This is a diagnostic register that is only valid when using the on-chip PCI Bus Arbiter. Reserved : Type : Initial value Reserved CPCIBRS : Type 0x80 : Initial value Bits Mnemonic...
Page 318: Pci Bus Arbiter Current State Register (Pbacstate) 0Xd11C
Chapter 10 PCI Controller 10.4.29 PCI Bus Arbiter Current State Register (PBACSTATE) 0xD11C This is a diagnostic register that is only valid when using the on-chip PCI Bus Arbiter. Reserved : Type : Initial value Reserved CPAS : Type 0x0000 : Initial value Bits Mnemonic...
Page 319: G2P Memory Space 0 G-Bus Base Address Register (G2Pm0Gbase) 0Xd120
Chapter 10 PCI Controller 10.4.30 G2P Memory Space 0 G-Bus Base Address Register (G2PM0GBASE) 0xD120 BA[31:16] : Type 0x0000 : Initial value BA[15:8] Reserved : Type 0x00 : Initial value Bits Mnemonic Field Name Description 31:8 BA[31:8] Base Address Base Address (Initial value: 0x0000_00, R/W) Sets the G-Bus base bus address of Memory Space 0 for initiator access.
Page 320: G2P Memory Space 1 G-Bus Base Address Register (G2Pm1Gbase) 0Xd128
Chapter 10 PCI Controller 10.4.31 G2P Memory Space 1 G-Bus Base Address Register (G2PM1GBASE) 0xD128 BA[31:16] : Type 0x0000 : Initial value BA[15:8] Reserved : Type 0x00 : Initial value Bits Mnemonic Field Name Description 31:8 BA[31:8] Memory Space Base Address (Initial value: 0x0000_00, R/W) Base Address 1 Sets the G-Bus base bus address of Memory Space 1 for initiator access.
Page 321: G2P Memory Space 2 G-Bus Base Address Register (G2Pm2Gbase) 0Xd130
Chapter 10 PCI Controller 10.4.32 G2P Memory Space 2 G-Bus Base Address Register (G2PM2GBASE) 0xD130 BA[31:16] : Type 0x0000/0x1FC0 : Initial value BA[15:8] Reserved : Type 0x00 : Initial value Bits Mnemonic Field Name Description Base Address (Initial value: Normal Mode: 0x0000_00; PCI Boot Mode: 0x1FC0_00, 31:8 BA[31:8] Base Address...
Page 322: G2P I/O Space G-Bus Base Address Register (G2Piogbase) 0Xd138
Chapter 10 PCI Controller 10.4.33 G2P I/O Space G-Bus Base Address Register (G2PIOGBASE) 0xD138 BA[31:16] : Type 0x0000 : Initial value BA[15:8] Reserved : Type 0x00 : Initial value Bits Mnemonic Field Name Description 31:8 BA[31:8] Base Address Base Address (Initial value: 0x0000_00, R/W) Sets the G-Bus base bus address of the I/O Memory Space for initiator access.
Page 323: G2P Memory Space 0 Address Mask Register (G2Pm0Mask) 0Xd140
Chapter 10 PCI Controller 10.4.34 G2P Memory Space 0 Address Mask Register (G2PM0MASK) 0xD140 Reserved AM[28:16] : Type 0x0000 : Initial value AM[15:8] Reserved : Type 0x00 : Initial value Bits Mnemonic Field Name Description ⎯ ⎯ 31:29 Reserved 28:8 AM[28:8] Address Mask G-Bus to PCI-Bus Address Mask (Initial value: 0x0000_00, R/W)
Page 324: G2P Memory Space 1 Address Mask Register (G2Pm1Mask) 0Xd144
Chapter 10 PCI Controller 10.4.35 G2P Memory Space 1 Address Mask Register (G2PM1MASK) 0xD144 Reserved AM[28:16] : Type 0x0000 : Initial value AM[15:8] Reserved : Type 0x00 : Initial value Bits Mnemonic Field Name Description ⎯ ⎯ 31:29 Reserved 28:8 AM[31:8] Address Mask G-Bus to PCI-Bus Address Mask (Initial value: 0x0000_00, R/W)
Page 325: G2P Memory Space 2 Address Mask Register (G2Pm2Mask) 0Xd148
Chapter 10 PCI Controller 10.4.36 G2P Memory Space 2 Address Mask Register (G2PM2MASK) 0xD148 Reserved AM[28:16] : Type 0x0000/0x003f : Initial value AM[15:8] Reserved : Type 0x00/0xFF : Initial value Bits Mnemonic Field Name Description ⎯ ⎯ 31:29 Reserved 28:8 AM[31:8] Address Mask G-Bus to PCI-Bus Address Mask (Initial value: 0x0000_00, R/W)
Page 326: G2P I/O Space Address Mask Register (G2Piomask) 0Xd14C
Chapter 10 PCI Controller 10.4.37 G2P I/O Space Address Mask Register (G2PIOMASK) 0xD14C Reserved AM[28:16] : Type 0x0000 : Initial value AM[15:8] Reserved : Type 0x00 : Initial value Bits Mnemonic Field Name Description ⎯ ⎯ 31:29 Reserved 28:8 AM[28:8] Address Mask G-Bus to PCI-Bus Address Mask (Initial value: 0x0000_00, R/W) Sets the bits to be subject to address comparison.
Page 327: G2P Memory Space 0 Pci Base Address Register (G2Pm0Pbase) 0Xd150
Chapter 10 PCI Controller 10.4.38 G2P Memory Space 0 PCI Base Address Register (G2PM0PBASE) 0xD150 BA[31:16] : Type 0x0000 : Initial value BA[15:8] Reserved : Type 0x00 : Initial value Bits Mnemonic Field Name Description 31:8 BA[31:8] Base Address Base Address (Initial value: 0x0000_00, R/W) Sets the PCI Base address of Memory Space 0 for initiator access.
Page 328: G2P Memory Space 1 Pci Base Address Register (G2Pm1Pbase) 0Xd158
Chapter 10 PCI Controller 10.4.39 G2P Memory Space 1 PCI Base Address Register (G2PM1PBASE) 0xD158 BA[31:16] : Type 0x0000 : Initial value BA[15:8] Reserved : Type 0x00 : Initial value Bits Mnemonic Field Name Description 31:8 BA[31:8] Base Address Base Address (Initial value: 0x0000_00, R/W) Sets the PCI Base address of Memory Space 1 for initiator access.
Page 329: G2P Memory Space 2 Pci Base Address Register (G2Pm2Pbase) 0Xd160
Chapter 10 PCI Controller 10.4.40 G2P Memory Space 2 PCI Base Address Register (G2PM2PBASE) 0xD160 BA[31:16] : Type 0x0000/0xBFC0 : Initial value BA[15:8] Reserved : Type 0x00 : Initial value Bits Mnemonic Field Name Description 31:8 BA[31:8] Base Address Base Address (Initial value: 0x0000_00/0xBFC0_00(if PCI boot), R/W) Sets the PCI Base address of Memory Space 2 for initiator access.
Page 330: G2P I/O Space Pci Base Address Register (G2Piopbase) 0Xd168
Chapter 10 PCI Controller 10.4.41 G2P I/O Space PCI Base Address Register (G2PIOPBASE) 0xD168 BA[31:16] : Type 0x0000 : Initial value BA[15:8] Reserved : Type 0x00 : Initial value Bits Mnemonic Field Name Description 31:8 BA[31:8] Base Address Base Address (Initial value: 0x0000_00, R/W) Sets the PCI Base address of the I/O Space for initiator access.
Page 331: Pci Controller Configuration Register (Pciccfg) 0Xd170
Chapter 10 PCI Controller 10.4.42 PCI Controller Configuration Register (PCICCFG) 0xD170 Reserved GBWC[19:16] : Type : Initial value GBWC[7:0] Reserved HRST SRST TCAR LCFG Reserved R/W : Type 0xff : Initial value Bits Mnemonic Field Name Description ⎯ ⎯ 31:20 Reserved 19:8 GBWC...
Page 332: Pci Controller Status Register (Pcicstatus) 0Xd174
Chapter 10 PCI Controller 10.4.43 PCI Controller Status Register (PCICSTATUS) 0xD174 Reserved : Type : Initial value Reserved SERR R/W1C : Type : Initial value Bits Mnemonic Field Name Description ⎯ ⎯ 31:1 Reserved SERR SERR* Detected SERR* Occurred (Initial value: 0, R/W1C) Indicates that the System Error signal (SERR*) was asserted.
Page 333: Pci Controller Interrupt Mask Register (Pcicmask) 0Xd178
Chapter 10 PCI Controller 10.4.44 PCI Controller Interrupt Mask Register (PCICMASK) 0xD178 Reserved : Type : Initial value Reserved SERRIE R/W : Type : Initial value Bits Mnemonic Field Name Description ⎯ ⎯ 31:1 Reserved SERRIE SERR* Detect SERR* Interrupt Enable (Initial value: 0, R/W) Interrupt Enable This bit generates an interrupt when the System Error signal (SERR*) is asserted.
Page 334: P2G Memory Space 0 G-Bus Base Address Register (P2Gm0Gbase) 0Xd180
Chapter 10 PCI Controller 10.4.45 P2G Memory Space 0 G-Bus Base Address Register (P2GM0GBASE) 0xD180 BA[31:20] Reserved : Type 0x000 : Initial value Reserved : Type : Initial value Bits Mnemonic Field Name Description 31:20 BA[31:20] Base Address Base Address 0 (Initial value: 0x000, R/W) Sets the G-Bus base bus address of Memory Space 0 for target access.
Page 335: P2G Memory Space 0 Control Register (P2Gm0Ctr) 0Xd184
Chapter 10 PCI Controller 10.4.46 P2G Memory Space 0 Control Register (P2GM0CTR) 0xD184 Reserved AM[28:20] Reserved : Type 0x03F : Initial value Reserved TPRBL Reserved TMCC BSWAP MEMOPD Reserved P2GM0EN R/W : Type : Initial value Bits Mnemonic Field Name Description ⎯...
Page 336: P2G Memory Space 1 G-Bus Base Address Register (P2Gm1Gbase) 0Xd188
Chapter 10 PCI Controller 10.4.47 P2G Memory Space 1 G-Bus Base Address Register (P2GM1GBASE) 0xD188 BM[31:20] Reserved : Type 0x000 : Initial value Reserved : Type : Initial value Bits Mnemonic Field Name Description Memory Space 31:20 BA[31:20] Base Address 0 (Initial value: 0x000, R/W) Base Address 1 Sets the G-Bus base bus address of Memory Space 1 for target access.
Page 337: P2G Memory Space 1 Control Register (P2Gm1Ctr) 0Xd18C
Chapter 10 PCI Controller 10.4.48 P2G Memory Space 1 Control Register (P2GM1CTR) 0xD18C Reserved AM[28:20] Reserved : Type 0x03F : Initial value Reserved TPRBL Reserved TMCC BSWAP Reserved MEM1PE P2GM1EN R/W : Type : Initial value Bits Mnemonic Field Name Description ⎯...
Page 338: P2G Memory Space 2 G-Bus Base Address Register (P2Gm2Gbase) 0Xd190
Chapter 10 PCI Controller 10.4.49 P2G Memory Space 2 G-Bus Base Address Register (P2GM2GBASE) 0xD190 BA[31:20] Reserved : Type 0x000 : Initial value Reserved : Type : Initial value Bits Mnemonic Field Name Description Memory Space 31:20 BA[31:20] Base Address 2 (Initial value: 0x000, R/W) Base Address 2 Sets the G-Bus base bus address of Memory Space 2 for target access.
Page 339: P2G Memory Space 2 Control Register (P2Gm2Ctr) 0Xd194
Chapter 10 PCI Controller 10.4.50 P2G Memory Space 2 Control Register (P2GM2CTR) 0xD194 Reserved AM[28:20] Reserved : Type 0x000 : Initial value Reserved TPRBL Reserved TMCC BSWAP Reserved MEM1PE P2GM1EN R/W : Type : Initial value Bits Mnemonic Field Name Description ⎯...
Page 340: P2G I/O Space G-Bus Base Address Register (P2Giogbase) 0Xd198
Chapter 10 PCI Controller 10.4.51 P2G I/O Space G-Bus Base Address Register (P2GIOGBASE) 0xD198 BA[31:16] : Type 0x0000 : Initial value BA[15:8] Reserved : Type 0x00 : Initial value Bits Mnemonic Field Name Description Memory Space 31:8 BA[31:8] Base Address 2 (Initial value: 0x0000_00, R/W) Base Address 2 Sets the G-Bus base bus address of the I/O Space for target access.
Page 341: P2G I/O Space Control Register (P2Gioctr) 0Xd19C
Chapter 10 PCI Controller 10.4.52 P2G I/O Space Control Register (P2GIOCTR) 0xD19C Reserved : Type : Initial value AM[15:8] Reserved BSWAP P2GIOEN R/W : Type 0x00 : Initial value Bits Mnemonic Field Name Description ⎯ ⎯ 31:16 Reserved 15:8 AM[15:8] Address Mask PCI-Bus to G-Bus Address Mask (Initial value: 0x00, R/W) Sets the bits to be subject to address comparison.
Page 342: G2P Configuration Address Register(G2Pcfgadrs) 0Xd1A0
Chapter 10 PCI Controller 10.4.53 G2P Configuration Address Register(G2PCFGADRS) 0xD1A0[m3] Reserved BUSNUM : Type 0x00 : Initial value DEVNUM REGNUM TYPE FNNUM : Type 0x00 0x00 : Initial value Bits Mnemonic Field Name Description ⎯ ⎯ 31:24 Reserved 23:16 BUSNUM Bus Number Bus Number (Initial value: 0x00, R/W) Indicates the target PCI Bus Number (one of 256).
Page 343: G2P Configuration Data Register (G2Pcfgdata) 0Xd1A4
Chapter 10 PCI Controller 10.4.54 G2P Configuration Data Register (G2PCFGDATA) 0xD1A4 This is the only register that supports Byte access and 16-bit Word access. The upper address bit of the PCI Configuration Space is specified by the G2P Configuration Address Register (G2PCFGADRS). The lower two bits of the address are specified by the lower two bits of the offset address in this register as shown in Table 10.4.2.
Page 344: G2P Interrupt Acknowledge Data Register (G2Pintack)0Xd1C8
Chapter 10 PCI Controller 10.4.55 G2P Interrupt Acknowledge Data Register (G2PINTACK)0xD1C8 IIACKD : Type ⎯ : Initial value IIACKD : Type ⎯ : Initial value Bits Mnemonic Field Name Description Initiator Interrupt 31:0 IIACKD Initiator Interrupt Acknowledge Address Port (Initial value: –, R) Acknowledge An Interrupt Acknowledge cycle is generated on the PCI Bus when this register is Address Port...
Page 345: G2P Special Cycle Data Register (G2Pspc) 0Xd1Cc
Chapter 10 PCI Controller 10.4.56 G2P Special Cycle Data Register (G2PSPC) 0xD1CC ISCD : Type ⎯ : Initial value ISCD : Type ⎯ : Initial value Bits Mnemonic Field Name Description Initiator Special 31:0 ISCD Initiator Special Cycle Data Port (Initial value: –, W) Cycle Data Port When this register is written to, Special Cycles are generated on the PCI Bus depending on the data that is written.
Page 346: Configuration Data 0 Register (Pcicdata0) 0Xd1E0
Chapter 10 PCI Controller 10.4.57 Configuration Data 0 Register (PCICDATA0) 0xD1E0 If PCICCFG.LCFG is set, a write to PCICDATA0, 1, 2 & 3 will modify the contents of the associated Configuration registers in the PCI Core. : Type 0x0181 : Initial value : Type 0x102F : Initial value...
Page 347: Configuration Data 1 Register (Pcicdata1) 0Xd1E4
Chapter 10 PCI Controller 10.4.58 Configuration Data 1 Register (PCICDATA1) 0xD1E4 : Type 0x0600 : Initial value : Type 0x00 : Initial value Bits Mnemonic Field Name Description 31:8 Class Code Class Code (Initial value: 0x0600_00, R/W) This is the data loaded in the Class Code Register of the PCI Configuration Space. Revision ID Revision ID (Initial value: –, R/W) This is the data loaded in the Revision ID Register of the PCI Configuration Space.
Page 348: Configuration Data 2 Register (Pcicdata2) 0Xd1E8
Chapter 10 PCI Controller 10.4.59 Configuration Data 2 Register (PCICDATA2) 0xD1E8 SSID : Type 0x0000 : Initial value SSVID : Type 0x0000 : Initial value Bits Mnemonic Field Name Description 31:16 SSID Sub System ID Subsystem ID (Initial value: 0x0000, R/W) This is the data loaded in the Sub System ID Register of the PCI Configuration space.
Page 349: Configuration Data 3 Register (Pcicdata3) 0Xd1Ec
Chapter 10 PCI Controller 10.4.60 Configuration Data 3 Register (PCICDATA3) 0xD1EC : Type 0x00 0x00 : Initial value : Type 0x00 0x00 : Initial value Bits Mnemonic Field Name Description Maximum 31:24 Max_Lat (Maximum Latency) (Initial value: 0x00, R/W) Latency This is the data loaded in the Max_Lat Register of the PCI Configuration Space.
Page 350: Pdmac Chain Address Register (Pdmca) 0Xd200
Chapter 10 PCI Controller 10.4.61 PDMAC Chain Address Register (PDMCA) 0xD200 PDMCA[31:16] : Type Undefined : Initial value PDMCA[15:2] Reserved : Type Undefined : Initial value Bits Mnemonic Field Name Description 31:2 PDMCA Chain Address PDMAC Chain Address (Initial value: undefined, R/W) The address of the next PDMAC Data Command Descriptor to be read is specified by a G-Bus physical address on a 32-bit address boundary.
Page 351: Pdmac G-Bus Address Register (Pdmga) 0Xd204
Chapter 10 PCI Controller 10.4.62 PDMAC G-Bus Address Register (PDMGA) 0xD204 PDMGA[31:16] : Type Undefined : Initial value PDMCA[15:2] Reserved : Type Undefined : Initial value Bits Mnemonic Field Name Description 31:2 PDMGA G-Bus Address PDMAC G-Bus Address (Initial value: undefined, R/W) The G-Bus DMA transfer address is specified by a G-Bus physical address on a 32-bit address boundary.
Page 352: Pdmac Pci Bus Address Register (Pdmpa) 0Xd208
Chapter 10 PCI Controller 10.4.63 PDMAC PCI Bus Address Register (PDMPA) 0xD208 PDMPA[31:16] : Type Undefined : Initial value PDMCA[15:2] Reserved : Type Undefined : Initial value Bits Mnemonic Field Name Description 31:2 PDMPA PCI Bus Address PDMAC PCI-Bus Address (Initial value: undefined, R/W) The PCI Bus DMA transfer address is specified by a PCI Bus physical address on a 32-bit address boundary.
Page 353: Pdmac Count Register (Pdmctr) 0Xd20C
Chapter 10 PCI Controller 10.4.64 PDMAC Count Register (PDMCTR) 0xD20C Reserved PDMCTR[23:16] : Type Undefined : Initial value PDMCTR[15:2] Reserved : Type Undefined : Initial value Bits Mnemonic Field Name Description ⎯ ⎯ 31:24 Reserved 23:2 PDMCTR Transfer Byte PDMAC Transfer Count (Initial value: undefined, R/W) Count Sets an uncoded 24-bit transfer byte count in 32-bit word units.
Page 354: Pdmac Configuration Register (Pdmcfg) 0Xd210
Chapter 10 PCI Controller 10.4.65 PDMAC Configuration Register (PDMCFG) 0xD210 Reserved Reserved RSTFIFO BSWAP GBRSTI : Type : Initial value Reserved REQDLY ERRIE Reserved XFRMODE CHRST CHNEN XFRACT NCCMPIE NTCMPIE XFRDIRC R/W : Type : Initial value Bits Mnemonic Field Name Description ⎯...
Page 355 Chapter 10 PCI Controller Bits Mnemonic Field Name Description CHNEN Chain Enable Chain Enable (Initial value: 0) (Read Only) When the current data transfer is complete, this field reads the next data command Descriptor from the address indicated by the PDMAC Chain Address Register then indicates whether to continue the transfer or not.
Page 356: Pdmac Status Register (Pdmstatus) 0Xd214
Chapter 10 PCI Controller 10.4.66 PDMAC Status Register (PDMSTATUS) 0xD214 Reserved FIFOCNT FIFOWP FIFORP : Type 00000 : Initial value Reserved PCIACT ERRINT CHNEN ACCMP NCCMP NTCMP PCIERR Reserved DONEINT XFRACT PCIPERR PCISERR CHNERR DATAERR R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C : Type : Initial value Bits Mnemonic...
Page 357 Chapter 10 PCI Controller Bits Mnemonic Field Name Description ⎯ ⎯ Reserved PCIPERR PCI Parity Error PCI Parity Error (Initial value: 0, R/W1C) 1: Indicates that there was a parity error on a PCI transaction performed on behalf of the PDMAC. 0: Indicates that no parity error has been detected on PDMAC PCI transfer since this bit was cleared.
Page 358: Pci Configuration Space Register
Chapter 10 PCI Controller 10.5 PCI Configuration Space Register The PCI Configuration Space Register is accessed using PCI Configuration cycles by way of an external PCI host device only when in the Satellite mode. Table 10.5.1 lists registers contained within the PCI Configuration Space Register.
Page 359: Capability Id Register (Cap_Id) 0Xdc
Chapter 10 PCI Controller 10.5.1 Capability ID Register (Cap_ID) 0xDC Reserved : Type 0x01 : Initial value Bits Mnemonic Field Name Description ⎯ ⎯ 15:8 Reserved Capability ID Capability ID (Initial value: 0x01, R) Indicates that a list is the link list of the Power Management Register. Figure 10.5.1 Capability ID Register 10-99...
Page 360: Next Item Pointer Register (Next_Item_Ptr) 0Xdd
Chapter 10 PCI Controller 10.5.2 Next Item Pointer Register (Next_Item_Ptr) 0xDD Reserved : Type 0x00 : Initial value Bits Mnemonic Field Name Description ⎯ ⎯ 15:8 Reserved Next Item Pointer Next Item Pointer (Initial value: 0x00, R) This is the Next Item pointer. Indicates the end of a list. Figure 10.5.2 Next Item Pointer Register 10-100...
Page 361: Power Management Capability Register (Pmc) 0Xde
Chapter 10 PCI Controller 10.5.3 Power Management Capability Register (PMC) 0xDE PMESPT D2SPT D1SPT Reserved PMVER Reserved PMECLK : Type 0x00 : Initial value Bits Mnemonic Field Name Description 15:11 PMESPT PME Output PME_ Support (Fixed value: 0x00, R) Support On TX4925 the function is not supported.
Page 362: Power Management Control/Status Register (Pmcsr) 0Xe0
Chapter 10 PCI Controller 10.5.4 Power Management Control/Status Register (PMCSR) 0xE0 Reserved Reserved PMEEN PMESTA : Type : Initial value Bits Mnemonic Field Name Description PMESTA PME Status PME_Status (Initial value: 0, R) On TX4925 the function is not supported. ⎯...
Page 363: Serial I/O Port
Chapter 11 Serial I/O Port 11. Serial I/O Port 11.1 Features The TX4925 asynchronous Serial I/O (SIO) interface has two full duplex UART channels (SIO0 and SIO1). SIO has the following features. • Full duplex transmission (simultaneous transmission and reception) •...
Page 364: Block Diagram
Chapter 11 Serial I/O Port 11.2 Block Diagram SCLK SIOCLK Baud Rate IMBUSCLK Baud Rate Control Register IM Bus Receiver RTS* Receive Data Receive Data Register FIFO Read Receiver Shift Buffer Register DMA/INT Control Register Interrupt I/F DMA/INT FIFO Control Status Register Register Read...
Page 365: Detailed Explanation
Chapter 11 Serial I/O Port 11.3 Detailed Explanation 11.3.1 Overview During reception, serial data that are input as an RXD signal from an external source are converted into parallel data, then are stored in the Receive FIFO buffer. Parallel data stored in the FIFO buffer are fetched by either CPU or DMA transfer.
Page 366 Chapter 11 Serial I/O Port 8-bit Data Transfer Direction stop bit2, parity Start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 Parity stop stop stop bit1, parity Start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 Parity stop stop bit2 Start bit0 bit1...
Page 367: Serial Clock Generator
Chapter 11 Serial I/O Port 11.3.3 Serial Clock Generator Generates the Serial Clock (SIOCLK). SIOCLK determines the serial transfer rate and has a frequency that is 16× the baud rate. One of the following can be selected as the source for the Serial Clock (SIOCLK).
Page 368 Chapter 11 Serial I/O Port Table 11.3.1 Example Divide Value Settings (and error [%] from target baud rate value) Prescalar Value (SIBGR.BLCK) and Divide Value (SIBGR.BRD) fc [MHz] kbps IMBUS 0.11 178 (−0.25 %) CLKF 0.15 130 (−0.16 %) 0.30 65 (0.16 %) 0.60 130 (0.16 %)
Page 369: Data Reception
Chapter 11 Serial I/O Port 11.3.4 Data Reception When the Serial Data Reception Disable bit (RSDE) of the Flow Control Register (SIFLCRn) is set to “0”, reception operation starts after the RXD signal start bit is detected. Start bits are detected when the RXD signal transitions from the High state to the Low state.
Page 370: Dma Transfer
Chapter 11 Serial I/O Port 11.3.6 DMA Transfer The DMA Request Control Register (DRQCTR)of the DMA Request Select field (DMAREQ[3:0]) can be used to allocate DMA channels for each reception and transmission channel in the following manner. SIO Channel 1 Reception DMA Channel 0 SIO Channel 1 Transmission DMA Channel 1...
Page 371: Reception Data Status
Chapter 11 Serial I/O Port 11.3.8 Reception Data Status Status data such as the following is also stored in the Receive FIFO. • Overrun error An overrun error is generated if all 16-stage Receive FIFO buffers become full and more data is transferred to the Reception Read buffer.
Page 372: Reception Time Out
Chapter 11 Serial I/O Port 11.3.9 Reception Time Out A Reception time out is detected and the Reception Time Out bit (TOUT) of the DMA/Interrupt Status Register (SIDISR) is set under the following conditions. • Non-DMA transfer mode (SIDICRn.RDE = 0): When at least 1 Byte of reception data exists in the Receive FIFO and the data reception time for the 2 frames (2 Bytes) after the last reception has elapsed •...
Page 373: Error Detection/Interrupt Signaling
Chapter 11 Serial I/O Port 11.3.11 Error Detection/Interrupt Signaling An interrupt is signaled if an error or an interrupt cause is detected, the corresponding status bit is set and the corresponding Interrupt Enable bit is set. Figure 11.3.3 shows the relationship between the status bit for each interrupt cause and each interrupt enable bit.
Page 374: Multi-Controller System
Chapter 11 Serial I/O Port 11.3.12 Multi-Controller System The Multi-Controller System consists of one Master Controller, and multiple Slave Controllers as shown below in Figure 11.3.4. In the case of the Multi-Controller System, the Master Controller transmits an address (ID) frame to all Slave Controllers, then transmits and receives data with the selected Slave Controller.
Page 375: Registers
Chapter 11 Serial I/O Port 11.4 Registers With the exception of DMA access to the Transmit FIFO Register or the Receive FIFO Register, please use Word access when accessing register in the Serial I/O Port. Table 11.4.1 SIO Registers Reference Offset Address Mnemonic Register Name...
Page 376: Line Control Register 0 (Silcr0) 0Xf300 (Ch. 0) Line Control Register 1 (Silcr1) 0Xf400 (Ch. 1)
Chapter 11 Serial I/O Port 11.4.1 Line Control Register 0 (SILCR0) 0xF300 (Ch. 0) Line Control Register 1 (SILCR1) 0xF400 (Ch. 1) These registers specify the format of asynchronous transmission/reception data. : Type : Initial value RWUB TWUB UODE UEPS UPEN USBL UMODE : Type : Initial value...
Page 377: Dma/Interrupt Control Register 0 (Sidicr0) 0Xf304 (Ch. 0) Dma/Interrupt Control Register 1 (Sidicr1) 0Xf404 (Ch. 1)
Chapter 11 Serial I/O Port 11.4.2 DMA/Interrupt Control Register 0 (SIDICR0) 0xF304 (Ch. 0) DMA/Interrupt Control Register 1 (SIDICR1) 0xF404 (Ch. 1) These registers use either DMA or interrupts to execute the Host Interface. : Type : Initial value SPIE CTSAC STIE : Type...
Page 378 Chapter 11 Serial I/O Port Bits Mnemonic Field Name Description STIE Status Change Status Change Interrupt Enable (Initial value: 000000, R/W) Interrupt Enable This field sets the set conditions of the Status Change bit (STIS) of the DMA/Interrupt Status Register (SIDISR). The condition is selected depending on which bit of the Status Change Interrupt Status Register (SISCISR) is set.
Page 379: Dma/Interrupt Status Register 0 (Sidisr0) 0Xf308 (Ch. 0) Dma/Interrupt Status Register 1 (Sidisr1) 0Xf408 (Ch. 1)
Chapter 11 Serial I/O Port 11.4.3 DMA/Interrupt Status Register 0 (SIDISR0) 0xF308 (Ch. 0) DMA/Interrupt Status Register 1 (SIDISR1) 0xF408 (Ch. 1) These registers indicate the DMA or interrupt status information. : Type : Initial value UBRK UFER UPER UOER TOUT TDIS RDIS STIS...
Page 380 Chapter 11 Serial I/O Port Bits Mnemonic Field Name Description STIS Status Change Status Change Interrupt Status (Initial value: 0, R/W0C) This bit is set when at least one of the interrupt statuses selected by the Status Change Interrupt Condition field (STIE) of the DMA/Interrupt Control Register (SIDICR) becomes “1”.
Page 381: Status Change Interrupt Status Register 0 (Siscisr0) 0Xf30C (Ch. 0) Status Change Interrupt Status Register 1 (Siscisr1) 0Xf40C (Ch. 1)
Chapter 11 Serial I/O Port 11.4.4 Status Change Interrupt Status Register 0 (SISCISR0) 0xF30C (Ch. 0) Status Change Interrupt Status Register 1 (SISCISR1) 0xF40C (Ch. 1) : Type : Initial value OERS CTSS TRDY TXALS RBRKD UBRKD R/W0C RW0C : Type CTS* : Initial value Bits...
Page 382: Fifo Control Register 0 (Sifcr0) 0Xf310 (Ch. 0) Fifo Control Register 1 (Sifcr1) 0Xf410 (Ch. 1)
Chapter 11 Serial I/O Port 11.4.5 FIFO Control Register 0 (SIFCR0) 0xF310 (Ch. 0) FIFO Control Register 1 (SIFCR1) 0xF410 (Ch. 1) These registers set control of the Transmit/Receive FIFO buffer. : Type : Initial value RDIL TDIL SWRST TFRST RFRST FRSTE R/W : Type : Initial value Bits...
Page 383: Flow Control Register 0 (Siflcr0) 0Xf314 (Ch. 0) Flow Control Register 1 (Siflcr1) 0Xf414 (Ch. 1)
Chapter 11 Serial I/O Port 11.4.6 Flow Control Register 0 (SIFLCR0) 0xF314 (Ch. 0) Flow Control Register 1 (SIFLCR1) 0xF414 (Ch. 1) : Type : Initial value RSDE TSDE RTSTL TBRK RTSSC R/W : Type 0001 : Initial value Bits Mnemonic Field Name Description...
Page 384 Chapter 11 Serial I/O Port 11.4.7 Baud Rate Control Register 0 (SIBGR0) 0xF318 (Ch. 0) Baud Rate Control Register 1 (SIBGR1) 0xF418 (Ch. 1) These registers select the clock that is provided to the baud rate generator and set the divide value. : Type : Initial value BCLK...
Page 385: Transmit Fifo Register 0 (Sitfifo0) 0Xf31C (Ch. 0) Transmit Fifo Register 1 (Sitfifo1) 0Xf41C (Ch. 1)
Chapter 11 Serial I/O Port 11.4.8 Transmit FIFO Register 0 (SITFIFO0) 0xF31C (Ch. 0) Transmit FIFO Register 1 (SITFIFO1) 0xF41C (Ch. 1) When using the DMA Controller to perform DMA transmission, set the following addresses in the Destination Address Register (DMDARn) of the DMA Controller according to the Endian Mode bit (DMCCRn.LE) setting of the DMA Controller.
Page 386: Receive Fifo Register 0 (Sirfifo0) 0Xf320 (Ch. 0) Receive Fifo Register 1 (Sirfifo1) 0Xf420 (Ch. 1)
Chapter 11 Serial I/O Port 11.4.9 Receive FIFO Register 0 (SIRFIFO0) 0xF320 (Ch. 0) Receive FIFO Register 1 (SIRFIFO1) 0xF420 (Ch. 1) When using the DMA Controller to perform DMA transmission, set the following addresses in the Destination Address Register (DMDARn) of the DMA Controller according to the Endian Mode bit (DMCCRn.LE) setting of the DMA Controller.
Page 387: Timer/Counter
Chapter 12 Timer/Counter 12. Timer/Counter 12.1 Features The TX4925 has an on-chip 3-channel timer/counter. • 32-bit Up Counter: 3 Channels • Interval Timer Mode (Channel 0, 1, 2) • Pulse Generator Mode (Channel 0, 1) • Watchdog Timer Mode (Channel 2) •...
Page 388: Block Diagram
Chapter 12 Timer/Counter 12.2 Block Diagram TX4925 IM-Bus I/F Signal TIMER[0] Timer-0 Counter Input Clock Interval Timer Mode Timer Interrupt 0 Timer-1 IM-Bus I/F Signal TIMER[1] Pulse Generator Mode Counter Input Clock Interval Timer Mode Timer Interrupt 1 IM-Bus I/F Signal Timer-2 Counter Input Clock Interval Timer Mode...
Page 389: Detailed Explanation
Chapter 12 Timer/Counter 12.3 Detailed Explanation 12.3.1 Overview The TX4925 has an on-chip 3-channel 32-bit timer/counter. Each channel supports the following modes. (1) Interval Timer Mode (Timer 0, 1, 2) This mode periodically generates interrupts. (2) Pulse Generator Mode (Timer 0, 1) This is the pulse signal output mode.
Page 390: Counter
Chapter 12 Timer/Counter 12.3.3 Counter Each channel has an independent 32-bit counter. Set the Timer Count Enable bit (TMTCRn.TCE) and the 32-bit counter will start counting. Clear the Timer Count Enable bit to stop the counter. If the Counter Reset Enable bit (TMTCRn.CRE) is set, then the counter will be cleared also.
Page 391 Chapter 12 Timer/Counter Count Value TMCPRA Reg. Compare Value 0x000000 Time TCE = 1 TCE = 0 TCE = 1 TCE = 0 TCE = 1 TCE = 0 CRE = 1 CRE = 0 CRE = 0 TZCE = 1 TZCE = 0 TZCE = 1 TIIE = 1 TIIE = 0 TIIE = 1...
Page 392: Pulse Generator Mode
Chapter 12 Timer/Counter 12.3.5 Pulse Generator Mode When in the Pulse Generator mode, use Compare Register A (TMCPRAn) and Compare Register B (TMCPRBn) to output a particular period and particular duty square wave to the TIMER[n] signal. Setting the Timer Mode field (TMTCRn.TMODE) of the Timer Control Register to “01” sets the timer to the Pulse Generator mode.
Page 393: Watchdog Timer Mode
Chapter 12 Timer/Counter 12.3.6 Watchdog Timer Mode The Watchdog Timer mode is used to monitor system anomalies. The software periodically clears the counter and judges an anomaly to exist if the counter is not cleared within a specified period of time. Then, either the TX4925 is internally reset or an NMI is signaled to the TX49/H2 core.
Page 394 Chapter 12 Timer/Counter The level of the TIMER[1:0] output signal when in this mode remains in the default state (Low). Output is undefined when the mode is changed from the Pulse Generator mode to this mode. Count Value TMCPRA2 Compare Value 0x000000 Time TCE = 1...
Page 395: Registers
Chapter 12 Timer/Counter 12.4 Registers Table 12.4.1 Timer Register List Reference Offset Address Bit Width Register Symbol Register Name Time 0 (TMR0) 12.4.1 0xF000 TMTCR0 Timer Control Register 0 12.4.2 0xF004 TMTISR0 Timer Interrupt Status Register 0 12.4.3 0xF008 TMCPRA0 Compare Register A 0 12.4.4 0xF00C...
Page 396: Timer Control Register N (Tmtcrn) Tmtcr0 0Xf000 Tmtcr1 0Xf100 Tmtcr2 0Xf200
Chapter 12 Timer/Counter 12.4.1 Timer Control Register n (TMTCRn) TMTCR0 0xF000 TMTCR1 0xF100 TMTCR2 0xF200 : Type : Initial value CCDE ECES TMODE : Type : Initial value Bits Mnemonic Field Name Description ⎯ ⎯ 31:8 Reserved Timer Counter Timer Count Enable (Initial value: 0, R/W) Enable This field controls whether the counter runs or stops.
Page 397: Timer Interrupt Status Register N (Tmtisrn) Tmtisr0 0Xf004 Tmtisr1 0Xf104 Tmtisr2 0Xf204
Chapter 12 Timer/Counter 12.4.2 Timer Interrupt Status Register n (TMTISRn) TMTISR0 0xF004 TMTISR1 0xF104 TMTISR2 0xF204 : Type : Initial value TWIS TPIBS TPIAS TIIS R/W0C R/W0C R/W0C R/W0C : Type : Initial value Bits Mnemonic Field Name Description ⎯ ⎯...
Page 398 Chapter 12 Timer/Counter 12.4.3 Compare Register An (TMCPRAn) TMCPRA0 0xF008 TMCPRA1 0xF108 TMCPRA2 0xF208 TCVA : Type 0xFFFF : Initial value TCVA : Type 0xFFFF : Initial value Bits Mnemonic Field Name Description 31:0 TCVA Timer Compare Timer Compare Value A (Initial value: 0xFFFF_FFFF, R/W) Register A Sets the timer compare value as a 32-bit value.
Page 399 Chapter 12 Timer/Counter 12.4.4 Compare Register Bn (TMCPRBn) TMCPRB0 0xF00C TMCPRB1 0xF10C TCVB : Type 0xFFFF : Initial value TCVB : Type 0xFFFF : Initial value Bits Mnemonic Field Name Description Timer Compare 31:0 TCVB Timer Compare Value B (Initial value: 0xFFFF_FFFF, R/W) Value B Sets the timer compare value as a 32-bit value.
Page 400: Tmitmr2 0Xf210
Chapter 12 Timer/Counter 12.4.5 Interval Timer Mode Register n (TMITMRn) TMITMR0 0xF010 TMITMR1 0xF110 TMITMR2 0xF210 : Type : Initial value TIIE TZCE R/W : Type : Initial value Bits Mnemonic Field Name Description ⎯ ⎯ 31:16 Reserved Interval Timer TIIE Timer Interval Interrupt Enable (Initial value: 0, R/W) Interrupt Enable...
Page 401 Chapter 12 Timer/Counter 12.4.6 Divide Register n (TMCCDRn) TMCCDR0 0xF020 TMCCDR1 0xF120 TMCCDR2 0xF220 : Type : Initial value : Type : Initial value Bits Mnemonic Field Name Description ⎯ ⎯ 31:3 Reserved Counter Clock Counter Clock Divide (Initial value: 000, R/W) Divide Value These bits specify the divide value when using the internal clock (IMBUSCLK) as the counter input clock source.
Page 402: Pulse Generator Mode Register N (Tmpgmrn) Tmpgmr0 0Xf030 Tmpgmr1 0Xf130
Chapter 12 Timer/Counter 12.4.7 Pulse Generator Mode Register n (TMPGMRn) TMPGMR0 0xF030 TMPGMR1 0xF130 : Type : Initial value TPIBE TPIAE R/W : Type : Initial value Bits Mnemonic Field Name Description ⎯ ⎯ 31:16 Reserved TPIBE TMCPRB Timer Pulse Generator Interrupt by TMCPRB Enable (Initial value: 0, R/W) Interrupt Enable When in the Pulse Generator mode, this bit sets Interrupt Enable/Disable for when TMCPRB and the counter value match.
Page 403: Watchdog Timer Mode Register N (Tmwtmrn) Tmwtmr2 0Xf240
Chapter 12 Timer/Counter 12.4.8 Watchdog Timer Mode Register n (TMWTMRn) TMWTMR2 0xF240 : Type : Initial value TWIE WDIS R/W1S R/W1C : Type : Initial value Bits Mnemonic Field Name Description ⎯ ⎯ 31:16 Reserved Watchdog Timer TWIE Timer Watchdog Enable (Initial value: 0, R/W) Signaling Enable This bit sets NMI signaling enable/disable either when in the Watchdog Timer mode or during a reset.
Page 404: Tmtrr2 0Xf2F0
Chapter 12 Timer/Counter 12.4.9 Timer Read Register n (TMTRRn) 0xF0F0 TMTRR0 0xF0F0 TMTRR1 0xF1F0 TMTRR2 0xF2F0 TCNT : Type 0x0000 : Initial value TCNT : Type 0x0000 : Initial value Bits Mnemonic Field Name Description 31:0 TCNT Timer Counter Timer Counter (Initial value: 0x0000_0000, R) This Read Only register is a 32-bit counter.
Page 405: Parallel I/O Port
Chapter 13 Parallel I/O Port 13. Parallel I/O Port 13.1 Characteristics The TX4925 on-chip Parallel I/O port (PIO) is a 16-bit general-purpose parallel port. The input/output direction and the port type during output (totem pole output/open drain output) can be set for each bit. 13.2 Block Diagram PIO[31:0] Other Function...
Page 406: Detailed Description
Chapter 13 Parallel I/O Port 13.3 Detailed Description 13.3.1 Selecting PIO Pins All of the 32-bit PIO signals are shared with other functions. The boot configuration signal (TDO) and pin configuration register (PCFG) determine which functions will be used. See Sections “3.2 Boot Configuration”, “3.3 Pin Multiplexing”...
Page 407: Pio Output Data Register (Piodo) 0Xf500
Chapter 13 Parallel I/O Port 13.4.1 PIO Output Data Register (PIODO) 0xF500 : Type 0x0000 : Initial value : Type 0x0000 : Initial value Bits Mnemonic Field Name Description 31:0 PDO [31:0] Data Out Port Data Output [31:0] (Initial value: 0x0000_0000, R/W) Data that is output to the PIO pin (PIO [31:0]).
Page 408: Pio Direction Control Register (Piodir) 0Xf508
Chapter 13 Parallel I/O Port 13.4.3 PIO Direction Control Register (PIODIR) 0xF508 PDIR : Type 0x0000 : Initial value PDIR : Type 0x0000 : Initial value Bits Mnemonic Field Name Description 31 :0 PDIR [31:0] Direction Control Port Direction Control [31:0] (Initial value: 0x0000_0000, R/W) Sets the I/O direction of the PIO pin (PIO [31:0]).
Page 409: Ac-Link Controller
Chapter 14 AC-link Controller 14. AC-link Controller 14.1 Features ACLC, AC-link controller module can be connected to audio and/or modem CODECs described in the “Audio CODEC ’97 Revision 2.1” (AC’97) defined by Intel and can operate them. Refer to the following Web site for more information regarding the AC’97 specification.
Page 410: Configuration
Chapter 14 AC-link Controller 14.2 Configuration Figure 14.2.1 illustrates the ACLC configuration. DMAC IM-bus aclcimbif Bus I/F System-side ACLC (imclk/imreset* ) Data I/O Master Slave Register Wakeup Control Asynchronous Handshake Slot-data Slot Valid/Req & Transfer Register Access Link-side (BITCLK/ACRESET* ) Bitstream Receive &...
Page 411: Functional Description
Chapter 14 AC-link Controller 14.3 Functional Description ACLC provides four mechanisms to operate AC’97-compliant CODEC(s): • AC-link status control (start-up and low-power mode) • CODEC register access • Sample-data transmission and reception • GPIO operation This section first describes the CODEC connection, chip configuration, and overall usage-flow. Then AC- link start-up sequence and the other mechanisms will be described.
Page 412: Pin Configuration
Chapter 14 AC-link Controller 14.3.1.2 5.1 Channel Audio Connection This sample assumes one CODEC with four DACs mapped to stereo front (3&4) and stereo rear (7&8) slots, and another CODEC with two DACs mapped to center (6) and LFE (9) slots. ACLC 4 Channel Audio CODEC (CODEC ID=’0’) SYNC...
Page 413: Usage Flow
Chapter 14 AC-link Controller 14.3.3 Usage Flow This section outlines a process flow when using the AC’97 connected to ACLC. Refer to the subsequent sections for the details of each operation performed in this process flow. The diagrams below describe the audio playback and recording processes. The modem transmission and reception can be done in a similar way.
Page 414 Chapter 14 AC-link Controller System Software ACLC and DMAC AC’97 Enable ENLINK Deassert ACRESET* Start BITCLK Set CODEC Ready CODECRDY Interrupt Check AC’97 status Start recording audio ADC Ready response Start up AC-link Register setting such as gain (*) Set gain, etc. Clear DMA buffer Configure DMAC Start DMA Channel and...
Page 415: Ac-Link Start Up
Chapter 14 AC-link Controller 14.3.4 AC-link Start Up Figure 14.3.5 shows the conceptual sequence of AC-link start-up. The ACLC Control Enable Register’s Enable AC-link bit is used to deassert/assert the ACRESET* signal to the link side (including AC-link). This bit defaults to ‘0’, so the CPU asserts the ACRESET* signal when it boots up.
Page 416: Codec Register Access
Chapter 14 AC-link Controller 14.3.5 CODEC Register Access By accessing registers in the CODEC, the system software is able to detect or control the CODEC state. This section describes how to read and write CODEC registers via ACLC. For details about AC’97 register set and proper sequence to operate CODEC, refer to the AC’97 specification and target CODEC datasheet.
Page 417: Sample-Data Transmission And Reception
Chapter 14 AC-link Controller 14.3.6 Sample-data Transmission and Reception This section describes the mechanism for transmission and reception of PCM audio and modem wave-data. An overview is described first. The DMA (Direct Memory Access) operation, error detection and recovery procedure follow. A special case using slot activation control is described last. 14.3.6.1 Overview Figure 14.3.6 and Figure 14.3.7 show conceptual views of the sample-data transmission and reception mechanisms.
Page 418 Chapter 14 AC-link Controller 14.3.6.2 DMA Channel Mapping ACLC uses four DMA request channels. These DMA channels are allocated to four out of seven data-streams, or slots, on the AC-link frame, according to ACLC DMA Channel Selection Register (ACDMASEL) setting as shown in Table 14.3.1. The pin configuration register allocates these DMA channels of ACLC to the DMAC (DMA controller) channels according to DMA Request Control Register (DRQCTR)’s DMA Request Selection (DMAREQ0-3) bits as described in section 5.2.8.
Page 419 Chapter 14 AC-link Controller Figures below show the format of DMA buffer for each type of DMA channel. #0, #1, … means the sample’s sequential number for the AC-link slot. Subscript ‘L’ means lower 8-bit of each sample and subscript ‘H’ means upper 8-bit. Table 14.3.2 Front and Surround DMA Buffer Format in Little-endian Mode Address offset Left#0...
Page 420 Chapter 14 AC-link Controller 14.3.6.4 DMA Operation When ACLC’s REQ latch (refer to Figure 14.3.6 and Figure 14.3.7) needs to read or write sample-data, it issues a DMA request. When DMAC acknowledges the request by performing write- or read-access to the ACLC sample-data register, ACLC deasserts the request. Therefore, the software must properly set up DMAC so that the source or destination points to the corresponding sample-data register for the DMA channel.
Page 421 Chapter 14 AC-link Controller 14.3.6.5 Sample-data FIFO For a transmission stream, as long as ACLC Control Enable Register (ACCTLEN) allows that transmission and the FIFO has any room to fill data in, the FIFO issues a request via the REQ latch.
Page 422: Gpio Operation
Chapter 14 AC-link Controller 14.3.6.7 Slot Activation Control In case ACLC is required to begin transmission or reception of multiple streams at the same time, slot activation control will be useful. To use this feature, the software must deactivate the relevant streams first, enable ACLC Control Enable Register (ACCTLEN), make sure the transmission FIFO becomes full by checking ACLC FIFO Status Register (ACFIFOSTS)’s Full (xxxxFULL) bit, and finally enable ACLC Slot Enable Register (ACSLTEN).
Page 423: Interrupt
Chapter 14 AC-link Controller 14.3.8 Interrupt ACLC generate two kinds of interrupt to the interrupt controller as below. • ACLC Interrupt Logical OR of all the valid bits of ACLC Interrupt Masked Status Register (ACINTMSTS) is connected. Refer to section 14.4.5. •...
Page 424: Registers
Chapter 14 AC-link Controller 14.4 Registers The base address for the ACLC registers is described in section 5.1.7. Only word (32-bit) accesses are allowed. These registers return to their initial values when the module gets reset by power-on or configuration-register operation. The ‘Disable AC-link’ operation initializes the ACREGACC, ACGPIDAT, ACGPODAT, and ACSLTEN registers while keeping the other registers.
Page 425: Aclc Control Enable Register (Acctlen) 0Xf700
Chapter 14 AC-link Controller 14.4.1 ACLC Control Enable Register (ACCTLEN) 0xF700 This register is used to check the setting of various ACLC features and to enable them. MODIE MODOE AUDIE LFEEH CENTE SURRE AUDO Reserved Reserved EHLT : Type R/W1S R/W1S R/W1S R/W1S R/W1S R/W1S R/W1S : Initial value MODID...
Page 426 Chapter 14 AC-link Controller Bits Mnemonic Field Name Description SURREHLT Enable Audio Enable Audio Surround L&R Transmit-data DMA Error Halt. (Initial value: 0, R/W1S) Surround L&R 0: Indicates that SURRDMA error halt is disabled. Transmit-data 1: Indicates that SURRDMA error halt is enabled. DMA Error Halt 0: No effect 1: Enables SURRDMA error halt.
Page 427 Chapter 14 AC-link Controller Bits Mnemonic Field Name Description ⎯ ⎯ Reserved RDYCLR Clear CODEC Clear CODEC Ready Bit (Initial value: 0, W1S) Ready Bit W1C 0: No effect 1: Clear CODEC[1:0] ready bits Note: This bit should only be written to reevaluate the CODEC ready status after power- down command is sent to CODEC.
Page 428: Aclc Control Disable Register (Acctldis) 0Xf704
Chapter 14 AC-link Controller 14.4.2 ACLC Control Disable Register (ACCTLDIS) 0xF704 This register is used to disable various ACLC features. MODIE MODO AUDIE LFEEH CENTE SURRE AUDO Reserved EHLT EHLT Reserved W1C : Type ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯...
Page 429 Chapter 14 AC-link Controller Bits Mnemonic Field Name Description ⎯ ⎯ Reserved AUDIDMA Disable Audio Disable Audio Receive-data DMA. (Initial value: –, W1C) Receive-data W1C 0: No effect 1: Disables audio receive-data DMA. Disable Audio LFEDMA Disable Audio LFE Transmit-data DMA. (Initial value: –, W1C) LFE Transmit- W1C 0: No effect data DMA...
Page 430: Aclc Codec Register Access Register (Acregacc) 0Xf708
Chapter 14 AC-link Controller 14.4.3 ACLC CODEC Register Access Register (ACREGACC) 0xF708 CODEC registers can be accessed through this register. CODE Reserved CODECID REGADR Reserved : Type ⎯ ⎯ 0x00 : Initial value REGDAT : Type 0x0000 : Initial value Bits Mnemonic Field Name...
Page 431: Aclc Interrupt Status Register (Acintsts) 0Xf710
Chapter 14 AC-link Controller 14.4.4 ACLC Interrupt Status Register (ACINTSTS) 0xF710 This register shows various kinds of AC-link and ACLC status. Reserved : Type : Initial value MODIE MODOE AUDIE CENTE SURRE AUDOE REGAC CODEC CODEC Reserved Reserved Reserved LFEERR GPIOINT CRDY 1RDY...
Page 432 Chapter 14 AC-link Controller Bits Mnemonic Field Name Description REGACCRDY ACREGACC ACREGACC Ready (Initial value: 1, R/W1C) Ready 1: Indicates that the ACREGACC register is ready to get the value (in case the previous operation was a read access) and to initiate another R/W access to an AC’97 register.
Page 433: Aclc Interrupt Masked Status Register (Acintmsts) 0Xf714
Chapter 14 AC-link Controller 14.4.5 ACLC Interrupt Masked Status Register (ACINTMSTS) 0xF714 Every bit in this register is configured as follows: ACINTMSTS = ACINTSTS & ACINTEN Bit placement is the same as for the ACINTSTS register. The logical OR of all bits in this register is used as ACLC interrupt request to the interrupt controller.
Page 434: Aclc Semaphore Register (Acsemaph) 0Xf720
Chapter 14 AC-link Controller 14.4.8 ACLC Semaphore Register (ACSEMAPH) 0xF720 This register is used for mutual exclusion control for resource. SEMAPH RS/WC : Type 0x0000 : Initial value SEMAPH RS/WC : Type 0x0000 : Initial value Bits Mnemonic Field Name Description SEMAPH Semaphore flag...
Page 435: Aclc Gpi Data Register (Acgpidat) 0Xf740
Chapter 14 AC-link Controller 14.4.9 ACLC GPI Data Register (ACGPIDAT) 0xF740 This register shows GPIO (slot 12) input data. Reserved GPIDAT : Type 0x00000 : Initial value GPIO GPIDAT : Type 0x00000 : Initial value Bits Mnemonic Field Name Description ⎯...
Page 436: Aclc Gpo Data Register (Acgpodat) 0Xf744
Chapter 14 AC-link Controller 14.4.10 ACLC GPO Data Register (ACGPODAT) 0xF744 This register specifies GPIO (slot 12) output data. Reserved GPODAT WRPEND : Type 0x00000 : Initial value GPODAT : Type 0x00000 : Initial value Bits Mnemonic Field Name Description ⎯...
Page 437: Aclc Slot Enable Register (Acslten) 0Xf748
Chapter 14 AC-link Controller 14.4.11 ACLC Slot Enable Register (ACSLTEN) 0xF748 This register enables independently the AC-link slot data streams. Reserved WRPEND : Type : Initial value MODO CENT SURR AUDO Reserved GPISLT GPOSLT MODISLT Reserved AUDISLT LFESLT : Type R/W1S R/W1S R/W1S R/W1S R/W1S R/W1S R/W1S R/W1S R/W1S : Initial value...
Page 438 Chapter 14 AC-link Controller Bits Mnemonic Field Name Description AUDISLT Enable Audio Enable Audio slot reception. (Initial value: 1, R/W1S) slot reception 0: Indicates that audio slot reception is disabled. 1: Indicates that audio slot reception is enabled. 0: No effect 1: Enables audio slot reception.
Page 439: Aclc Slot Disable Register (Acsltdis) 0Xf74C
Chapter 14 AC-link Controller 14.4.12 ACLC Slot Disable Register (ACSLTDIS) 0xF74C This register disables independently the AC-link slot data streams. Reserved : Type : Initial value MODI MODO AUDI CENT SURR AUDO Reserved GPISLT GPOSLT Reserved LFESLT W1C : Type ⎯...
Page 440: Aclc Fifo Status Register (Acfifosts) 0Xf750
Chapter 14 AC-link Controller 14.4.13 ACLC FIFO Status Register (ACFIFOSTS) 0xF750 This register indicates the AC-link slot data FIFO status. Reserved : Type : Initial value MODO CENT SURR AUDO MODI MODO AUDI CENT SURR AUDO Reserved Reserved Reserved LFEFILL FULL FULL FULL...
Page 441 Chapter 14 AC-link Controller Bits Mnemonic Field Name Description CENTFILL Audio Center Audio Center Transmit-data Filled. (Initial value: 0, R) Transmit-data 0: Indicates audio Center transmit-data FIFO is empty. Filled 1: Indicates audio Center transmit-data FIFO is not empty. SURRFILL Audio Surround Audio Surround L&R Transmit-data Filled.
Page 442: Aclc Dma Request Status Register (Acdmasts) 0Xf780
Chapter 14 AC-link Controller 14.4.14 ACLC DMA Request Status Register (ACDMASTS) 0xF780 This register indicates the AC-link slot data DMA request status. Reserved : Type : Initial value MODI MODO AUDI CENT SURR AUDO Reserved Reserved LFEREQ : Type : Initial value Bits Mnemonic Field Name...
Page 443: Aclc Dma Channel Selection Register (Acdmasel) 0Xf784
Chapter 14 AC-link Controller 14.4.15 ACLC DMA Channel Selection Register (ACDMASEL) 0xF784 This register is used to select and check the channel allocation for AC-link slot data DMA. Reserved : Type : Initial value Reserved ACDMASEL : Type : Initial value Bits Mnemonic Field Name...
Page 444: Aclc Surround Data Register (Acaudodat)
Chapter 14 AC-link Controller 14.4.16 ACLC Surround Data Register (ACAUDODAT) 0xF7A0 ACLC Audio PCM Output Data Register (ACSURRDAT) 0xF7A4 These registers are used to write audio PCM L&R and surround L&R output data. DAT1: Sample Right (Little-endian mode) / DAT0: Sample Left (Big-endian mode) : Type : Initial value DAT0: Sample Left (Little-endian mode) / DAT1: Sample Right (Big-endian mode)
Page 445 Chapter 14 AC-link Controller 14.4.17 ACLC Center Data Register (ACCENTDAT) 0xF7A8 ACLC LFE Data Register (ACLFEDAT) 0xF7AC ACLC Audio PCM Input Data Register (ACMODODAT) 0xF7B8 This registers are used to write audio center, LFE, and modem output data. DAT1: Sample data 1 (Little-endian mode) / DAT0: Sample data 0 (Big-endian mode) : Type : Initial value DAT0: Sample data 0 (Little-endian mode) / DAT1: Sample data 1 (Big-endian mode)
Page 446: Aclc Modem Output Data Register (Acaudidat) 0Xf7B0
Chapter 14 AC-link Controller 14.4.18 ACLC Modem Output Data Register (ACAUDIDAT) 0xF7B0 This register is used to read audio PCM L&R input data. DAT1: Sample Right or ‘0’ (Little-endian mode) / DAT0: Sample Left or MIC (Big-endian mode) : Type Undefined : Initial value DAT0: Sample Left or MIC (Little-endian mode) / DAT1: Sample Right or ‘0’...
Page 447: Aclc Modem Input Data Register (Acmodidat) 0Xf7Bc
Chapter 14 AC-link Controller 14.4.19 ACLC Modem Input Data Register (ACMODIDAT) 0xF7BC This register is used to read modem input data. DAT1: Sample data 1 (Little-endian mode) / DAT0: Sample data 0 (Big-endian mode) : Type Undefined : Initial value DAT0: Sample data 0 (Little-endian mode) / DAT1: Sample data 1 (Big-endian mode) : Type Undefined...
Page 448: Aclc Revision Id Register (Acrevid) 0Xf7Fc
31:16 Reserved ⎯ ⎯ 15:8 Major Revision Contact Toshiba technical staff for an explanation of the revision value. ⎯ ⎯ Minor Revision Contact Toshiba technical staff for an explanation of the revision value. Figure 14.4.17 ACREVID Register This read-only register shows the revision of ACLC module. Note that this number is not related to the AC’97 specification revision.
Page 449: Interrupt Controller
Chapter 15 Interrupt Controller 15. Interrupt Controller 15.1 Characteristics The TX4925 on-chip Interrupt Controller (IRC) receives interrupt requests from the TX4925 on-chip peripheral circuitry as well as external interrupt requests then generates interrupt requests to the TX49/H2 processor core. Also, the Interrupt Controller has a 32-bit flag register that generates interrupt requests to either external devices or to the TX49/H2 core.
Page 450: Block Diagram
Chapter 15 Interrupt Controller 15.2 Block Diagram TX49/H2 Core External Interrupt Signal (INT[7:0]) Interrupt Controller Internal Timer TX49 Write Time Out Error Interrupt Request Interrupt Detection Circuit Request NAND Flash Controller (IP[7:2]) [7:2] SIO[1:0] Set Interrupt Level [6:2] DMA[3:0] Internal PDMAC Set Interrupt Mask Interrupt...
Page 451 Chapter 15 Interrupt Controller Interrupt Detection Interrupt Level Interrupt Mask Interrupt Detection Mode IRDM0-1 IRLVL0-7 Level IRMSK Enable IRDEN.IDE Detection Circuit Level Interrupt Source High Level Interrupt Encoder IP[7] Negative Prioritization Interrupt Edge Edge IRCS.FL Detector Interrupt Positive Pending Edge IRPND Edge IP[6:2]...
Page 452: Detailed Explanation
Chapter 15 Interrupt Controller 15.3 Detailed Explanation 15.3.1 Interrupt Sources The TX4925 has as interrupt sources interrupts from 21 types of on-chip peripheral circuits and 8 external interrupt signals. Table 15.3.1 lists the interrupt sources. Signals with the lower interrupt number have the higher priority.
Page 453: Interrupt Request Detection
Chapter 15 Interrupt Controller 15.3.2 Interrupt Request Detection In order to perform interrupt detection, each register of the Interrupt Controller is initialized, then the IDE bit of the Interrupt Detection Enable Register (IRDEN) is set to “1.” All interrupts detected by the Interrupt Controller are masked when this bit is cleared.
Page 454: Interrupt Notification
Chapter 15 Interrupt Controller Priorities are assigned as follows. • When interrupt levels differ, the interrupt with the higher interrupt level has priority (Table 15.3.2) • When multiple interrupts with the same interrupt level are simultaneously detected, the interrupt with the smaller interrupt number has priority (Table 15.3.1). In addition, the interrupt priority assignments are reevaluated under the following conditions.
Page 455: Clearing Interrupt Requests
Chapter 15 Interrupt Controller Table 15.3.3 Interrupt Notification to IP[7:2] of the CP0 Cause Register TINTDIS IP[7] IP[6:3] IP[2] Internal Timer IRCS.CAUSE[3:0] IRCS.IF (Internal Timer Interrupts: Valid) Interrupt Notification IRCS.CAUSE[4:0] IRCS.IF (Internal Timer Interrupts: Invalid) 15.3.6 Clearing Interrupt Requests Interrupt requests are cleared according to the following process. •...
Page 456: Registers
Chapter 15 Interrupt Controller IRRCNT.INTPOL IRFLAG[31] Internal Interrupt IRPOL[31] Request (0: Request present) IRMASK[31] External Interrupt Request IRRCNT.EXTPOL Figure 15.3.1 External Interrupt Request Logic There are two flag registers: Flag Register 0 (IRFLAG0), and Flag Register 1 (IRFLAG1). These registers have two different Write methods. Accordingly, Writes to one register are reflects in the other. Either “0”...
Page 457: Interrupt Detection Enable Register (Irden) 0Xf600
Chapter 15 Interrupt Controller 15.4.1 Interrupt Detection Enable Register (IRDEN) 0xF600 Reserved : Type : Initial value Reserved : Type : Initial value Bits Mnemonic Field Name Explanation ⎯ ⎯ 31:1 Reserved Interrupt Interrupt Detection Enable (Initial value: 0, R/W) Detection Enable Enables interrupt detection.
Page 458: Interrupt Detection Mode Register 0 (Irdm0) 0Xf604
Chapter 15 Interrupt Controller 15.4.2 Interrupt Detection Mode Register 0 (IRDM0) 0xF604 IC23 IC22 IC21 IC20 IC19 IC18 IC17 IC16 : Type : Initial value Reserved : Type : Initial value Bits Mnemonic Field Name Explanation Interrupt Source Interrupt Source Control 23 (Initial value: 00, R/W) 31:30 IC23 Control 23...
Page 459 Chapter 15 Interrupt Controller Bits Mnemonic Field Name Explanation 17:16 IC16 Interrupt Source Interrupt Source Control 16 (Initial value: 00, R/W) Control 16 These bits specify the active state of DMA[2] interrupts. 00: Low level active 01: Disable 10: Disable 11: Disable 15:14 Interrupt Source...
Page 460: Interrupt Detection Mode Register 1 (Irdm1) 0Xf608
Chapter 15 Interrupt Controller 15.4.3 Interrupt Detection Mode Register 1 (IRDM1) 0xF608 Reserved IC30 IC29 IC28 IC27 IC26 IC25 IC24 : Type : Initial value IC15 IC14 IC13 IC12 IC11 Reserved : Type : Initial value Bits Mnemonic Field Name Explanation ⎯...
Page 461 Chapter 15 Interrupt Controller Bits Mnemonic Field Name Explanation 15:14 IC15 Interrupt Source Interrupt Source Control 15 (Initial value: 00, R/W) Control 15 These bits specify the active state of DMA[1] interrupts. 00: Low level active 01: Disable 10: Disable 11: Disable 13:12 IC14...
Page 462: Interrupt Level Register 0 (Irlvl0) 0Xf610
Chapter 15 Interrupt Controller 15.4.4 Interrupt Level Register 0 (IRLVL0) 0xF610 Reserved IL17 Reserved IL16 : Type : Initial value Reserved Reserved : Type : Initial value Bits Mnemonic Field Name Explanation ⎯ ⎯ 31:27 Reserved 26:24 IL17 Interrupt Level 17 Interrupt Level of INT[17] (Initial value: 000, R/W) These bits specify the interrupt level of DMA[3] interrupts.
Page 463: Interrupt Level Register 1 (Irlvl1) 0Xf614
Chapter 15 Interrupt Controller 15.4.5 Interrupt Level Register 1 (IRLVL1) 0xF614 Reserved IL19 Reserved IL18 : Type : Initial value Reserved Reserved : Type : Initial value Bits Mnemonic Field Name Explanation ⎯ ⎯ 31:27 Reserved 26:24 IL19 Interrupt Level 19 Interrupt Level of INT[19] (Initial value: 000, R/W) These bits specify the interrupt level of PDMAC interrupts.
Page 464: Interrupt Level Register 2 (Irlvl2) 0Xf618
Chapter 15 Interrupt Controller 15.4.6 Interrupt Level Register 2 (IRLVL2) 0xF618 Reserved IL21 Reserved IL20 : Type : Initial value Reserved Reserved : Type : Initial value Bits Mnemonic Field Name Explanation ⎯ ⎯ 31:11 Reserved 26:24 IL21 Interrupt Level 21 Interrupt Level of INT[21] (Initial value: 000, R/W) These bits specify the interrupt level of TMR[0].
Page 465: Interrupt Level Register 3 (Irlvl3) 0Xf61C
Chapter 15 Interrupt Controller 15.4.7 Interrupt Level Register 3 (IRLVL3) 0xF61C Reserved IL23 Reserved IL22 : Type : Initial value Reserved Reserved : Type : Initial value Bits Mnemonic Field Name Explanation ⎯ ⎯ 31:27 Reserved 26:24 IL23 Interrupt Level 23 Interrupt Level of INT[23] (Initial value: 000, R/W) These bits specify the interrupt level of TMR[2].
Page 466: Interrupt Level Register 4 (Irlvl4) 0Xf620
Chapter 15 Interrupt Controller 15.4.8 Interrupt Level Register 4 (IRLVL4) 0xF620 Reserved IL25 Reserved IL24 : Type : Initial value Reserved Reserved : Type : Initial value Bits Mnemonic Field Name Explanation ⎯ ⎯ 31:27 Reserved Interrupt Level of INT[25] (Initial value: 000, R/W) 26:24 IL25 Interrupt level 25...
Page 467: Interrupt Level Register 5 (Irlvl5) 0Xf624
Chapter 15 Interrupt Controller 15.4.9 Interrupt Level Register 5 (IRLVL5) 0xF624 Reserved IL27 Reserved IL26 : Type : Initial value Reserved IL11 Reserved : Type : Initial value Bits Mnemonic Field Name Explanation ⎯ ⎯ 31:27 Reserved 26:24 IL27 Interrupt Level 27 Interrupt Level of INT[27] (Initial value: 000, R/W) These bits specify the interrupt level of ACLCPME interrupts.
Page 468: Interrupt Level Register 6 (Irlvl6) 0Xf628
Chapter 15 Interrupt Controller 15.4.10 Interrupt Level Register 6 (IRLVL6) 0xF628 Reserved IL29 Reserved IL28 : Type : Initial value Reserved IL13 Reserved IL12 : Type : Initial value Bits Mnemonic Field Name Explanation ⎯ ⎯ 31:27 Reserved 26:24 IL29 Interrupt Level 29 Interrupt Level of INT[29] (Initial value: 000, R/W) These bits specify the interrupt level of PCIERR interrupts.
Page 469: Interrupt Level Register 7 (Irlvl7) 0Xf62C
Chapter 15 Interrupt Controller 15.4.11 Interrupt Level Register 7 (IRLVL7) 0xF62C Reserved IL30 : Type : Initial value Reserved IL15 Reserved IL14 : Type : Initial value Bits Mnemonic Field Name Explanation ⎯ ⎯ 31:19 Reserved 18:16 IL30 Interrupt Level 30 Interrupt Level of INT[30] (Initial value: 000, R/W) These bits specify the interrupt level of PCIPME interrupts.
Page 470: Interrupt Mask Level Register (Irmsk) 0Xf640
Chapter 15 Interrupt Controller 15.4.12 Interrupt Mask Level Register (IRMSK) 0xF640 Reserved : Type : Initial value Reserved : Type : Initial value Bits Mnemonic Field Name Explanation ⎯ ⎯ 31:3 Reserved Interrupt Mask Interrupt Mask Level (Initial value: 000, R/W) Level These bits specify the interrupt mask level.
Page 471: Interrupt Edge Detection Clear Register (Iredc) 0Xf660
Chapter 15 Interrupt Controller 15.4.13 Interrupt Edge Detection Clear Register (IREDC) 0xF660 Reserved : Type : Initial value Reserved Reserved EDCS0 EDCE0 R/W1C : Type 0000 : Initial value Bits Mnemonic Field Name Explanation ⎯ ⎯ 31:9 Reserved Edge Detection Edge Detection Clear Enable 0 (Initial value: 0, R/W1C) EDCE0 Clear Enable 0...
Page 472 Chapter 15 Interrupt Controller 15.4.14 Interrupt Pending Register (IRPND) 0xF680 Indicates the status of each interrupt request regardless of the IRLVL 7-0 and IRMSK value. IS30 IS29 IS28 IS27 IS26 IS25 IS24 IS23 IS22 IS21 IS20 IS19 IS18 IS17 IS16 Reserved : Type : Initial value...
Page 473 Chapter 15 Interrupt Controller Bits Mnemonic Field Name Explanation IS20 Interrupt Status 20 IRINTREQ[20] status (Initial value: 0, R) This bit indicates the PCIC interrupt status. 1: Interrupt requests 0: No interrupt requests IRINTREQ[19] status (Initial value: 0, R) IS19 Interrupt Status 19 This bit indicates the PDMAC interrupt status.
Page 474 Chapter 15 Interrupt Controller Bits Mnemonic Field Name Explanation Interrupt Status 5 IRINTREQ[5] status (Initial value: 0, R) This bit indicates the status of external INT[3] interrupts. 1: Interrupt requests 0: No interrupt requests IRINTREQ[4] status (Initial value: 0, R) Interrupt Status 4 This bit indicates the status of external INT[2] interrupts.
Page 475: Interrupt Current Status Register (Ircs) 0Xf6A0
Chapter 15 Interrupt Controller 15.4.15 Interrupt Current Status Register (IRCS) 0xF6A0 Reserved : Type : Initial value Reserved Reserved CAUSE : Type 11111 : Initial value Bits Mnemonic Field Name Explanation ⎯ ⎯ 31:17 Reserved Interrupt Flag (Initial value: 1, R) Interrupt Flag This bit indicates the interrupt generation status.
Page 476 Chapter 15 Interrupt Controller Bits Mnemonic Field Name Explanation CAUSE Interrupt Cause Interrupt Cause (Initial value: 0x1F, R) These bits specify the interrupt cause that was reported to the TX49/H2 core. The values of these bits are undefined when there is no interrupt request. 00000: (Reserved) 00001: TX49 Write Timeout Error 00010: External INT[0] interrupt...
Page 477: Interrupt Request Flag Register 0 (Irflag0) 0Xf510
Chapter 15 Interrupt Controller 15.4.16 Interrupt Request Flag Register 0 (IRFLAG0) 0xF510 [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] : Type 0x0000 : Initial value [15] [14] [13] [12] [11] [10] : Type 0x0000 : Initial value...
Page 478: Interrupt Request Polarity Control Register (Irpol) 0Xf518
Chapter 15 Interrupt Controller 15.4.18 Interrupt Request Polarity Control Register (IRPOL) 0xF518 [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] : Type 0x0000 : Initial value [15] [14] [13] [12] [11] [10] : Type 0x0000 : Initial value...
Page 479: Interrupt Request Internal Interrupt Mask Register (Irmaskint) 0Xf520
Chapter 15 Interrupt Controller 15.4.20 Interrupt Request Internal Interrupt Mask Register (IRMASKINT) 0xF520 MINT MINT MINT MINT MINT MINT MINT MINT MINT MINT MINT MINT MINT MINT MINT MINT [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18]...
Page 480 Chapter 15 Interrupt Controller 15-32...
Page 481: Chi Module
Chapter 16 CHI Module 16. CHI Module 16.1 Characteristics The CHI Module within the TX4925 contains holding registers, shift registers, DMA support, and other logic to support interfacing to external full-duplex serial TDM communication peripherals, including ISDN communication devices and PCM/TDM serial highways. The TX4925 implementation of the CHI Module is based on the Concentration Highway Interface standard specified by Intel and AT&T, which is intended to allow glueless interface to various TDM highways used by numerous commercial products.
Page 482: Block Diagram
Chapter 16 CHI Module 16.2 Block Diagram See Figure 16.2.1 for a block diagram of the CHI Module. The CHI Module consists of holding registers (both transmit and receive), shift registers (both transmit and receive), DMA support, and other logic to support interfacing to various types of TDM highways. Data from DMA or CPU Control From CPU 32B TX Hold REG-A...
Page 483: Detailed Explanation
Chapter 16 CHI Module 16.3 Detailed Explanation 16.3.1 Transmitter For the CHI transmit direction, Buffer-A and Buffer-B transmit holding registers are written either from the DMA circuit or directly from the CPU. Each of these 2 holding registers are 32-bits wide, and CHI control logic determines which byte from which holding register gets loaded at a given time into the 8-bit transmit shift register.
Page 484: Receiver
Chapter 16 CHI Module 16.3.2 Receiver For the CHI receive direction, Buffer-A and Buffer-B receive holding registers are read either by the DMA circuit or directly by the CPU. Each of these 2 holding registers are 32 bits wide, and CHI control logic determines which byte to which holding register gets loaded at a given time from the 8-bit receive shift register.
Page 485 Chapter 16 CHI Module The programmable receive channel counter output is constantly compared with the receive TDM switch control register values, and whenever a match occurs, the byte of data is loaded from the receive shift register into the correct field within the receive holding register. Similarly, the programmable transmit channel counter output is constantly compared with the transmit TDM switch control register values, and whenever a match occurs, the byte of data is loaded from the correct field within the transmit holding register into the receive shift register.
Page 486: Dma Address Generation
Chapter 16 CHI Module 16.3.4 DMA Address Generation The CHI Module provides support for 2 full-duplex DMA channels: receive and transmit. The circuit used to generate the DMA address, as well as half-buffer and end-of-buffer interrupts is shown in Figure 16.3.3.
Page 487 Chapter 16 CHI Module Note that the byte lanes are swapped between the little- and big-endian modes. In the little-endian mode, bits 31:24 of a word on the DMA buffer correspond to the byte lane with the address offset ‘+3’ and therefore to the ‘byte0’...
Page 488: Timing Diagram
Chapter 16 CHI Module 16.3.5 Timing Diagram Figure 16.3.4 shows timing diagram for DMA transfer. ENCHI (*) CHIFS Hi-Z Ch.A TX Data#1 Ch.B TX Data#1 Ch.A TX Data#2 Ch.B TX Data#2 Ch.A TX Data#3 Ch.B TX Data#3 CHIDOUT Discarded Data Ch.A RX Data#1 Ch.B RX Data#1 Ch.A RX Data#2...
Page 489: Interrupts
Chapter 16 CHI Module 16.3.6 Interrupts The CHI module has eight types interrupt sources. OR signal of them connects to the internal Interrupt Controller (IRC). Please check CHI Interrupt Status Register (CHIINT) to know which type of interrupt occurred. Type Status Bits Mask-able Bit CHIBUSERROR...
Page 490: Frame Structure And Serial Timing
Chapter 16 CHI Module 16.3.7 Frame Structure and Serial Timing Each CHI frame (nominally 8 kHz rate) is time-division-multiplexed into several timeslots or channels. The total number of timeslots per frame is programmable, with a maximum of 64 timeslots allowed, and the number of timeslots is also restricted to an even number. Each timeslot is 8 bits, although 16-bit or 32-bit channels can be supported by accessing adjacent timeslots.
Page 491 Chapter 16 CHI Module Table 16.3.2 and Table 16.3.3 shows a summary matrix for the values of CERX and CETX for all possible settings of CHIRXBOFF and CHITXBOFF, respectively. These values are shown for various configurations of CHICLK mode (1x versus 2x), CHIFSEDGE, CHIRXEDGE, and CHITXEDGE. The CHIFSEDGE settings determine whether to use the rising edge (CHIFSEDGE = 1) or falling edge (CHIFSEDGE = 0) of CHICLK to sample CHIFS.
Page 492 Chapter 16 CHI Module channel 1 Start Frame start channel 0 channel 1 channel 63 CHICLK CHIFS CHIDIN CHIDOUT Figure 16.3.5 CHI Frame Structure Example CHICLK 1X mode CHIFS sampled on falling edge CHIDIN sampled on falling edge; RXBOFF = 0; CERX = 0 CHIDOUT pushed on rising edge;...
Page 493 Chapter 16 CHI Module Frame start channel 1 Start channel 63 channel 0 channel 1 CHICLK CHIFS CHIDIN CHIDOUT Figure 16.3.7 CHI Frame Structure Example CHICLK 1X mode CHIFS sampled on falling edge CHIDIN sampled on rising edge; RXBOFF = 2; CERX = 3 CHIDOUT pushed on falling edge;...
Page 494 Chapter 16 CHI Module channel 1 Start Frame start channel 63 channel 0 channel 1 CHICLK CHIFS CHIDIN CHIDOUT Figure 16.3.9 CHI Frame Structure Example CHICLK 2X mode CHIFS sampled on falling edge CHIDIN sampled on rising edge; RXBOFF = 2; CERX = 5 CHIDOUT pushed on rising edge;...
Page 495 Chapter 16 CHI Module channel 1 Start Frame start channel 63 channel 0 channel 1 CHICLK CHIFS CHIDIN CHIDOUT Figure 16.3.11 CHI Frame Structure Example CHICLK 2X mode CHIFS sampled on falling edge CHIRXFSPOL = 1 (negative polarity) CHIDIN sampled on rising edge; RXBOFF = 1; CERX = 3 CHIDOUT pushed on rising edge;...
Page 496: Configurations
Chapter 16 CHI Module 16.3.8 Configurations The programmability of the clock, sync, bit offsets, and number of timeslots allows the CHI Module to support a wide range of configurations. Several of these configurations are commonly utilized as communication interfaces by numerous commercial products, some of which are briefly discussed below.
Page 497: Registers
Chapter 16 CHI Module 16.4 Registers All registers should be accessed only as full word (32-bit) accesses. Any other type of access produces an undefined result. Please write “0” to the undefined bit. Table 16.4.1 CHI Module Registers Reference Offset Address Bit Width Register Symbol Register Name...
Page 498: Chi Control Register (Ctrl) 0Xa800
Chapter 16 CHI Module 16.4.1 CHI Control Register (CTRL) 0xA800 Reserved LOOP TEST FDIR FWID CHAN TBOF : Type 00000 0000 : Initial value RBOF TMSB RMSB RFPL TFPL REDG TEDG FEDG TFED R/W : Type 0000 : Initial value Bits Mnemonic Field Name...
Page 499 Chapter 16 CHI Module Bits Mnemonic Field Name Description RXMSBFIRST RMSB RXMSBFIRST bit (Initial value: 0, R/W) This bit selects between MSB-first and LSB-first serial data formats for each byte of the CHI receive data. 0: LSB-first 1: MSB-first CHIRXFSPOL RFPL CHIRXFSPOL bit (Initial value: 0, R/W) This bit selects between positive (active high) or negative (active low) polarity for...
Page 500 Chapter 16 CHI Module Bits Mnemonic Field Name Description CHITXEN CHITXEN bit (Initial value: 0, R/W) This bit is used to enable/disable CHI transmit processing in the direct CPU read/write mode, where the CPU writes the data to be transmitted through the CHI TX holding register.
Page 501: Chi Pointer Enable Register (Pntren) 0Xa804
Chapter 16 CHI Module 16.4.2 CHI Pointer Enable Register (PNTREN) 0xA804 TB3E TB2E TB1E TB0E TA3E TA2E TA1E TA0E RB3E RB2E RB1E RB0E RA3E RA2E RA1E RA0E R/W : Type : Initial value Reserved : Type : Initial value Bits Mnemonic Field Name Description...
Page 502 Chapter 16 CHI Module Bits Mnemonic Field Name Description RB3E CHIRXPTRB3EN CHIRXPTRB3EN bit (Initial value: 0, R/W) This bit is used to enable/disable the timeslot for the receive channel pointed to by the TDM switch pointer CHIRXPTRB3 0: Disable 1: Enable RB2E CHIRXPTRB2EN CHIRXPTRB2EN bit (Initial value: 0, R/W)
Page 503: Chi Receive Pointer A Register (Rxptra) 0Xa808
Chapter 16 CHI Module 16.4.3 CHI Receive Pointer A Register (RXPTRA) 0xA808 Reserved RXPTRA3 Reserved RXPTRA2 : Type 00000 00000 : Initial value Reserved RXPTRA1 Reserved RXPTRA0 : Type 00000 00000 : Initial value Bits Mnemonic Field Name Description ⎯ ⎯...
Page 504: Chi Receive Pointer B Register (Rxptrb) 0Xa80C
Chapter 16 CHI Module 16.4.4 CHI Receive Pointer B Register (RXPTRB) 0xA80C Reserved RXPTRB3 Reserved RXPTRB2 : Type 00000 00000 : Initial value Reserved RXPTRB1 Reserved RXPTRB0 : Type 00000 00000 : Initial value Bits Mnemonic Field Name Description ⎯ ⎯...
Page 505: Chi Transmit Pointer A Register (Txptra) 0Xa810
Chapter 16 CHI Module 16.4.5 CHI Transmit Pointer A Register (TXPTRA) 0xA810 Reserved TXPTRA3 Reserved TXPTRA2 : Type 00000 00000 : Initial value Reserved TXPTRA1 Reserved TXPTRA0 : Type 00000 00000 : Initial value Bits Mnemonic Field Name Description ⎯ ⎯...
Page 506: Chi Transmit Pointer B Register (Txptrb) 0Xa814
Chapter 16 CHI Module 16.4.6 CHI Transmit Pointer B Register (TXPTRB) 0xA814 Reserved TXPTRB3 Reserved TXPTRB2 : Type 00000 00000 : Initial value Reserved TXPTRB1 Reserved TXPTRB0 : Type 00000 00000 : Initial value Bits Mnemonic Field Name Description ⎯ ⎯...
Page 507: Chi Size Register (Chisize) 0Xa818
Chapter 16 CHI Module 16.4.7 CHI SIZE Register (CHISIZE) 0xA818 Reserved DCNT Reserved : Type 000000000000 : Initial value B1TM DLOP SIZE RDEN TDEN R/W : Type 000000000000 : Initial value Bits Mnemonic Field Name Description ⎯ ⎯ 31:30 Reserved 29:18 DCNT[13:2] CHIDMACNT...
Page 508: Chi Rx Start Register (Rxstrt) 0Xa81C
Chapter 16 CHI Module 16.4.8 CHI RX Start Register (RXSTRT) 0xA81C CHIRXSTART : Type 0000000000000000 : Initial value CHIRXSTART Reserved : Type 00000000000000 : Initial value Bits Mnemonic Field Name Description 31:2 RxStrt[31:2] CHIRXSTART CHIRXSTART bits (Initial value: 30’b0, W) These bits define the start address for the CHI RX DMA buffer.
Page 509: Chi Tx Start Register (Txstrt) 0Xa820
Chapter 16 CHI Module 16.4.9 CHI TX Start Register (TXSTRT) 0xA820 CHITXSTART : Type 0000000000000000 : Initial value CHITXSTART Reserved : Type 00000000000000 : Initial value Bits Mnemonic Field Name Description 31:2 TxStrt[31:2] CHITXSTART CHITXSTART bits (Initial value: 30’b0, W) These bits define the start address for the CHI TX DMA buffer.
Page 510: Chi Tx Holding Register (Chihold) 0Xa824
Chapter 16 CHI Module 16.4.10 CHI TX Holding Register (CHIHOLD) 0xA824 CHITXHOLD : Type 0000000000000000 : Initial value CHITXHOLD : Type 0000000000000000 : Initial value Bits Mnemonic Field Name Description 31:0 CHIHOLD[31:0] CHITXHOLD CHITXHOLD bits (Initial value: 32’b0, W) These bits represent the CHI data to be transmitted. CHI data can be either written directly to this register by the CPU or transparently read from the CHI TX DMA buffer to this register.
Page 511: Chi Rx Holding Register (Chihold) 0Xa824
Chapter 16 CHI Module 16.4.11 CHI RX Holding Register (CHIHOLD) 0xA824 CHIRXHOLD : Type 0000000000000000 : Initial value CHIRXHOLD : Type 0000000000000000 : Initial value Bits Mnemonic Field Name Description 31:0 CHIHOLD[31:0] CHIRXHOLD CHIRXHOLD bits (Initial value: 32’b0, R) These bits represent the CHI data to be received. CHI data can be either read directly from this register by the CPU or transparently written to the CHI RX DMA buffer from this register.
Page 512 Chapter 16 CHI Module 16.4.12 CHI Clock Register (CHICLOCK) 0xA828 Reserved : Type : Initial value Reserved CDIR MCLK CDIV : Type 00000000 : Initial value Bits Mnemonic Field Name Description ⎯ ⎯ 31:10 Reserved CDIR CHICLKDIR CHICLKDIR bit (Initial value: 0, R/W) This bit controls the direction of the CHICLK pin.
Page 513: Hi Interrupt Enable Register (Chiinte) 0Xa82C
Chapter 16 CHI Module 16.4.13 HI Interrupt Enable Register (CHIINTE) 0xA82C Reserved : Type : Initial value Reserved BUSIE 05IE 10IE DCIE INAIE INBIE ACTIE ERRIE : Type 00000000 : Initial value Bits Mnemonic Field Name Description ⎯ ⎯ 31:8 Reserved BUSIE CHIBUSERROR...
Page 514: Chi Interrupt Status Register (Chiint) 0Xa830
Chapter 16 CHI Module 16.4.14 CHI Interrupt Status Register (CHIINT) 0xA830 Reserved : Type : Initial value Reserved BUSI INAI INBI ACTI ERRI : Type 00000000 : Initial value Bits Mnemonic Field Name Description ⎯ ⎯ 31:8 Reserved BUSI CHIBUSERROR CHIBUSERROR Interrupt status bit (Initial value: 0, R/W) Interrupt Status This bit shows the CHIBUSERROR Interrupt Status.
Page 515: Serial Peripheral Interface
Chapter 17 Serial Peripheral Interface 17. Serial Peripheral Interface 17.1 Characteristics The SPI is a serial interface consisting of clock, data out, and data in. The SPI is used to interface to devices such as serial power supplies, serial A/D converters, and other devices that contain simple serial clock and data interface.
Page 516: Block Diagram
Chapter 17 Serial Peripheral Interface 17.2 Block Diagram The SPI Module primarily consists of a 16-bit SPI Data Register (SPDR), a 16-bit Shift Register, a 16-bit Transmitter Buffer, a 16-bit Receiver Buffer, a Baud Rate Generator, an Inter Frame Time Counter, and Interrupt Logic.
Page 517: Detailed Explanation
Chapter 17 Serial Peripheral Interface 17.3 Detailed Explanation 17.3.1 Operation mode There are 2 operation modes possible: • Configuration mode (OPMODE = ‘01’) : Only in this mode it is possible to change the setting of the low byte (bit 7 to 0) in the SPI Control Register 0 (SPCR0) and all bits in the SPI Control Register 1 (SPCR1).
Page 518: Baud Rate Generator
Chapter 17 Serial Peripheral Interface At the end of every series of transmission the software is supposed to negate the chip select signal for the target device by the following procedure. (1) Check if SRRDY or RBSI is a logic “1”. If not, do nothing. (2) Check if SIDLE is a logic “1”.
Page 519: Transfer Format
Chapter 17 Serial Peripheral Interface 17.3.4 Transfer Format During a SPI transfer, data is simultaneously transmitted (shifted out serially) and received serially (shifted in serially). The serial clock synchronizes shifting and sampling of the information on the two serial data lines. The transfer format depends on the setting of the SPHA and SPOL bits in the SPI Control Register 0 (SPCR0).
Page 520: Inter Frame Space Counter
Chapter 17 Serial Peripheral Interface 17.3.4.2 SPHA Equals 1 Format Figure 17.3.2 shows the transfer format for a SPHA=1 transfer. SPICLK (SPOL=0) SPICLK (SPOL=1) SPIIN SPIOUT Sample Point Figure 17.3.2 Transfer format when SPHA is “1”. In this transfer format, the value on the SPIIN and SPIOUT signals changes with the second clock edge on SPICLK.
Page 521: Spi Buffer Structure
Chapter 17 Serial Peripheral Interface 17.3.6 SPI Buffer Structure The SPI has both transmit and receive buffer. The buffers are implemented as FIFO and are able to store four frames each. When a new SPI transfer is started by writing the data register, the transfer value is first stored in SPI’s transmit buffer.
Page 522: Registers
Chapter 17 Serial Peripheral Interface 17.4 Registers All registers in the SPI Module should be accessed only as full word (32-bit) accesses. Any other type of access produces an undefined result. Please write “0” to the undefined bit. Table 17.4.1 SPI Module Registers Reference Address Bit Width...
Page 523: Spi Master Control Register (Spmcr) 0Xf800
Chapter 17 Serial Peripheral Interface 17.4.1 SPI Master Control Register (SPMCR) 0xF800 Reserved : Type : Initial value Reserved OPMODE Reserved BCLR SPSTP Reserved : Type : Initial value Bits Mnemonic Field Name Explanation ⎯ ⎯ 31 : 8 Reserved Operation Mode (Initial value: 01, R/W) OPMODE Operation Mode...
Page 524: Spi Control Register 0 (Spcr0) 0Xf804
Chapter 17 Serial Peripheral Interface 17.4.2 SPI Control Register 0 (SPCR0) 0xF804 Reserved : Type : Initial value TXIFL RXIFL SILIE SOEIE RBFIE TBFIE Reserved SBOS SPHA SPOL IFSPSE Reserved R/W : Type : Initial value Bits Mnemonic Field Name Explanation ⎯...
Page 525 Chapter 17 Serial Peripheral Interface Bits Mnemonic Field Name Explanation IFSPSE Inter Frame Inter Frame Space prescaler Enable (Initial value: 0, R/W) Space prescaler Enable the Inter Frame Space prescaler. enable 0: Disable 1: Enable ⎯ ⎯ Reserved SBOS SPI Bit Order SPI Bit Order Select (Initial value: 0, R/W) Select bit order of transfer data.
Page 526 Chapter 17 Serial Peripheral Interface 17.4.3 SPI Control Register 1 (SPCR1) 0xF808 Reserved : Type : Initial value Reserved : Type 0x00 00000 : Initial value Bits Mnemonic Field Name Explanation ⎯ ⎯ 31:16 Reserved SPI Data Rate (Initial value: 0x00, R/W) 15:8 SPI Data Rate Control the bit-rate for the transmission.
Page 527: Spi Inter Frame Space Register (Spfs) 0Xf80C
Chapter 17 Serial Peripheral Interface 17.4.4 SPI Inter Frame Space Register (SPFS) 0xF80C Reserved : Type : Initial value Reserved : Type 0000000000 : Initial value Bits Mnemonic Field Name Explanation ⎯ ⎯ 31:10 Reserved Inter Frame Inter Frame Space (Initial value: 0000000000b, R/W) Space Configure the amount of time, which is inserted between two consecutive frames.
Page 528: Spi Status Register (Spsr) 0Xf814
Chapter 17 Serial Peripheral Interface 17.4.5 SPI Status Register (SPSR) 0xF814 Reserved : Type : Initial value TBSI RBSI SPOE Reserved IFSD SIDLE STRDY SRRDY : Type : Initial value Bits Mnemonic Field Name Explanation ⎯ ⎯ 31:16 Reserved Transmit Buffer Transmit Buffer Status Indicator (Initial value: 1, R) TBSI Status Indicator...
Page 529 Chapter 17 Serial Peripheral Interface Bits Mnemonic Field Name Explanation IFSD SPI Inter Frame SPI Inter Frame Space Delay Indicator (Initial value: 0, R) Space Delay This flag is asserted during the time, where one frame has been processed and the Indicator next frame is being delayed by the inter-frame-space timer.
Page 530: Spi Data Register (Spdr) 0Xf818
Chapter 17 Serial Peripheral Interface 17.4.6 SPI Data Register (SPDR) 0xF818 Reserved : Type : Initial value : Type 0x00 : Initial value Bits Mnemonic Field Name Explanation ⎯ ⎯ 31:16 Reserved SPI Data Register SPI Data Register (Initial value: 0x00, R/W) 15:0 A write to the SPDR register writes the value to the transmit buffer.
Page 531: Nand Flash Memory Controller
Chapter 18 NAND Flash Memory Controller 18. NAND Flash Memory Controller 18.1 Characteristics The TX4925 on-chip NAND Flash Memory Controller (NDFMC) generates the control signals required to interface with the NAND Flash Memory. It has also the ECC calculating circuits. The NAND Flash Memory Controller has the following characteristics.
Page 532: Detailed Explanation
Chapter 18 NAND Flash Memory Controller 18.3 Detailed Explanation 18.3.1 Access to NAND Flash Memory The TX4925 NDFMC supports the interface between the NAND Flash Memory using register indirect sequence. It has the ECC calculating circuits. Please see 18.3.2 in detail of the ECC. This section describes the procedure to access to NAND Flash Memory.
Page 533 Chapter 18 NAND Flash Memory Controller (5) Write 16 bytes redundant data • NDFMCR (0xC004): Set 0x90 to do the data mode without ECC. • NDFDTR (0xC000): Write 16 bytes redundant data. D520: LPR[23:16] D521: LPR[31:24] D522: CPR[11:6], 2’b11 D525: LPR[7:0] D526: LPR[15:8] D527: CPR[5:0], 2’b11 (6) Run Page Program...
Page 534: Ecc Control
Chapter 18 NAND Flash Memory Controller (3) Read ECC data • NDFMCR (0xC004): Set 0x50 to do the ECC data read mode. • NDFDTR (0xC000): Read 6 bytes ECC data. First data: LPR[7:0] Second data: LPR[15:8] Third data: CPR[5:0], 2’b11 Fourth data: LPR[23:16] Fifth data:...
Page 535: Registers
Chapter 18 NAND Flash Memory Controller 18.4 Registers Table 18.4.1 NAND Flash Memory Control Registers Reference Address Bit Width Register Register Name 18.4.1 0xC000 NDFDTR NAND Flash memory Data transfer Register 18.4.2 0xC004 NDFMCR NAND Flash memory Mode Control Register 18.4.3 0xC008 NDFSR...
Page 536: Nand Flash Memory Mode Control Register (Ndfmcr) 0Xc004
Chapter 18 NAND Flash Memory Controller 18.4.2 NAND Flash Memory Mode Control Register (NDFMCR) 0xC004 Reserved : Type : Initial value Reserved BSPRT Reserved R/W : Type : Initial value Bits Mnemonic Field Name Description ⎯ ⎯ 31:8 Reserved Write Enable (Initial value: 0, R/W) Write Enable This bit enables the data write operation.
Page 537: Nand Flash Memory Status Register (Ndfsr) 0Xc008
Chapter 18 NAND Flash Memory Controller 18.4.3 NAND Flash Memory Status Register (NDFSR) 0xC008 Reserved : Type : Initial value Reserved BUSY Reserved : Type ⎯ : Initial value Bits Mnemonic Field Name Description ⎯ ⎯ 31:8 Reserved BUSY (Initial value: undefined, R) BUSY BUSY This bit shows the status of NAND flash memory.
Page 538: Nand Flash Memory Interrupt Status Register (Ndfisr) 0Xc00C
Chapter 18 NAND Flash Memory Controller 18.4.4 NAND Flash Memory Interrupt Status Register (NDFISR) 0xC00C Reserved : Type : Initial value Reserved : Type : Initial value Bits Mnemonic Field Name Description ⎯ ⎯ 31:1 Reserved Ready (Initial value: 0) Ready This bit is set when ND_RB* signal changes from Low to High if MRDY in NDFIMR is one.
Page 539: Nand Flash Memory Interrupt Mask Register (Ndfimr) 0Xc010
Chapter 18 NAND Flash Memory Controller 18.4.5 NAND Flash Memory Interrupt Mask Register (NDFIMR) 0xC010 Reserved : Type : Initial value Reserved INTEN Reserved MRDY R/W : Type : Initial value Bits Mnemonic Field Name Description ⎯ ⎯ 31:8 Reserved Interrupt Enable (Initial value: 0, R/W) INTEN Interrupt Enable...
Page 540: Nand Flash Memory Strobe Pulse Width Register (Ndfspr) 0Xc014
Chapter 18 NAND Flash Memory Controller 18.4.6 NAND Flash Memory Strobe Pulse Width Register (NDFSPR) 0xC014 Reserved : Type : Initial value Reserved HOLD : Type 0000 0000 : Initial value Bits Mnemonic Field Name Description ⎯ ⎯ 31:8 Reserved Hold Time (Initial value: 0000) HOLD Hold Time...
Page 541: Nand Flash Memory Reset Register (Ndfrstr) 0Xc018
Chapter 18 NAND Flash Memory Controller 18.4.7 NAND Flash Memory Reset Register (NDFRSTR) 0xC018 Reserved : Type : Initial value Reserved : Type : Initial value Bits Mnemonic Field Name Description ⎯ ⎯ 31:1 Reserved Reset (Initial value: 0, R/W) Reset Setting this bit reset the NANDFC.
Page 542: Timing Diagrams
Chapter 18 NAND Flash Memory Controller 18.5 Timing Diagrams 18.5.1 Command and Address Cycle NDFMCR.ALE = 0 NDFSPR.HOLD NDFSPR.SPW NDFMCR.CLE = 0 NDFMCR.ALE = 1 NDFMCR.CLE = 1 NDFMCR.CE = 1 Figure 18.5.1 Command and Address Cycle (NDFMCR.BSPRT = 0) 18-12...
Page 543: Data Read Cycle
Chapter 18 NAND Flash Memory Controller 18.5.2 Data Read Cycle GBUSCLK ND_CLE ND_ALE ND_CE* ND_RE* NDFSPR.SPW=0x4 NDFSPR.HOLD=0x2 ND_WE* ND_RB* BUSSPRT* DATA[7:0] TX4925 latches data from NAND flash. Figure 18.5.2 Data Read Cycle (NDFMCR.BSPRT = 0) 18-13...
Page 544 Chapter 18 NAND Flash Memory Controller GBUSCLK ND_CLE ND_ALE ND_CE* ND_RE* NDFSPR.SPW=0x4 NDFSPR.HOLD=0x2 ND_WE* ND_RB* BUSSPRT* DATA[7:0] TX4925 latches data from NAND flash. Figure 18.5.3 Data Read Cycle (NDFMCR.BSPRT = 1) 18-14...
Page 545: Data Write Cycle
Chapter 18 NAND Flash Memory Controller 18.5.3 Data Write Cycle GBUSCLK ND_CLE ND_ALE ND_CE* ND_RE * ND_WE* NDFSPR.SPW=0x3 NDFSPR.HOLD=0x2 ND_RB* BUSSPRT* DATA[7:0] TX4925 places data on the bus. Figure 18.5.4 Data Write Cycle 18-15...
Page 546: Example Of Using Nand Flash Memory
Chapter 18 NAND Flash Memory Controller 18.6 Example of Using NAND Flash Memory Figure 18.6.1 shows an example connection of NAND flash memory. BUSSPRT* is asserted when you read NAND flash memory. When connecting NAND flash memory to a Data Bus that performs bidirectional control using BUSSPRT*, connect to the TX4925’s DATA via a buffer as shown below.
Page 547: Real Time Clock (Rtc)
Chapter 19 Real Time Clock (RTC) 19. Real Time Clock (RTC) 19.1 Features Real Time Clock (RTC) is a 44-bit counter that uses a 32.768 kHz clock. The counter will provide a maximum count of 6213 days. Also includes is a 44-bit alarm register for the RTC that allows the software to set an alarm at any desired count of the RTC counter.
Page 548: Block Diagrams
Chapter 19 Real Time Clock (RTC) 19.2 Block Diagrams Figure 19.2.1 shows the RTC Block Diagram. ALARM[43:0] 4 Bit Ripple Counter 8 Bit Ripple Counter 8 Bit ALARMINT Ripple Counter 8 Bit Ripple Counter 8 Bit Ripple Counter 8 Bit Ripple C32K Counter...
Page 549: Operations
Chapter 19 Real Time Clock (RTC) 19.3 Operations 19.3.1 Operation The RTC contains five 8-bit ripple counters connected in series. The first counter counts on each C32K clock, while each successive counter only counts when the previous count stage has reached a count of “0xFF”.
Page 550: Rtc Register (High) (Rtchi) 0Xf900
Chapter 19 Real Time Clock (RTC) 19.4.1 RTC Register (High) (RTCHI) 0xF900 Reserved : Type : Initial value Reserved RTCHI : Type ⎯ : Initial value Bits Mnemonic Field Name Explanation ⎯ ⎯ 31:12 Reserved 11:0 RTCHI RTC Register RTC Register (High) (Initial value: undefined, R) (High) These bits provide the status of the bit 43 to 32 of RTC counter.
Page 551: Alarm Register (High) (Alarmhi) 0Xf908
Chapter 19 Real Time Clock (RTC) 19.4.3 Alarm Register (High) (ALARMHI) 0xF908 Reserved : Type : Initial value Reserved ALARMHI : Type 0x000 : Initial value Bits Mnemonic Field Name Explanation ⎯ ⎯ 31:12 Reserved 11:0 ALARMHI Alarm Register Alarm Register (High) (Initial value: 0x000, R/W) (High) These bits provide the status of the bit 43 to 32 of Alarm counter.
Page 552: Rtc Control Register (Rtcctrl) 0Xf910
Chapter 19 Real Time Clock (RTC) 19.4.5 RTC Control Register (RTCCTRL) 0xF910 Reserved : Type : Initial value Reserved FRZPRE FRZRTC RTCCLR Reserved TSTCLK RTCTST DISRTINT DISALINT R/W : Type : Initial value Bits Mnemonic Field Name Explanation ⎯ ⎯ 31:8 Reserved DISRTINT...
Page 553: Rtc Interrupt Status Register (Rtcint) 0Xf914
Chapter 19 Real Time Clock (RTC) 19.4.6 RTC Interrupt Status Register (RTCINT) 0xF914 Reserved : Type : Initial value Reserved RTCINT ALARMINT R/W : Type : Initial value Bits Mnemonic Field Name Explanation ⎯ ⎯ 31:2 Reserved RTCINT RTC Interrupt RTC Interrupt Status (Initial value: 0, R/W) Status This bit shows the RTC Interrupt Status.
Page 554 Chapter 19 Real Time Clock (RTC) 19-8...
Page 555: Removed
Chapter 20 Removed 20. Removed 20-1...
Page 556 Chapter 20 Removed 20-2...
Page 557: Extended Ejtag Interface
Execution control (run, break, step, register/memory access) • Real-time PC tracing Please contact your local Toshiba Sales representative for more information regarding how to connect the emulation probe. The two functions of the Extended EJTAG Interface operate in one of two modes.
Page 558: Jtag Boundary Scan Test
This section explains only those portions that are unique to the TX4925. Please refer to the TX49/H2 Core Architecture Manual for all other portion not covered here. Please contact your local Toshiba Sales representative for more information regarding the required BSDL files when performing the JTAG Boundary Scan Test.
Page 559: Instruction Register
Chapter 21 Extended EJTAG Interface 21.2.2 Instruction Register The JTAG Instruction Register consists of an 8-bit shift register. This register is used for selecting either one or both of the test to be performed and the Test Data Register to be accessed. The Data Register is selected according to the instruction code in Table 21.2.1.
Page 560 Chapter 21 Extended EJTAG Interface Table 21.2.2 TX4925 Processor JTAG Scan Sequence (1/2) JTAG Scan JTAG Scan JTAG Scan Signal Name Signal Name Signal Name Sequence Sequence Sequence PCIAD[14] PIO[8] GNT[0] * PCIAD[9] PIO[9] PCICLKIO PCIAD[10] PIO[12] PCICLK[1] PCIAD[11] PIO[17] PCICLK[2] C_BE[0] PIO[13]...
Page 561 Chapter 21 Extended EJTAG Interface Table 21.2.2 TX4925 Processor JTAG Scan Sequence (2/2) JTAG Scan JTAG Scan JTAG Scan Signal Name Signal Name Signal Name Sequence Sequence Sequence DATA[14] ADDR[10] SDCLKIN RP * ADDR[11] PIO[20] DATA[31] ADDR[12] PON * DQM[0] ADDR[13] PIO[19] CAS *...
Page 562: Device Id Register
Chapter 21 Extended EJTAG Interface 21.2.4 Device ID Register The Device ID Register is a 32-bit shift register. This register is used for reading the ID code that expresses the IC manufacturer, part number, and version from the IC and sending it to a serial device. The following figure shows the configuration of the Device ID Register.
Page 563: Initializing The Extended Ejtag Interface
Chapter 21 Extended EJTAG Interface 21.3 Initializing the Extended EJTAG Interface The Extended EJTAG Interface is not reset by asserting the RESET* signal. Operation of the TX49/H2 core is not guaranteed if the Extended EJTAG Interface is not reset. This interface is initialized by either of the following methods.
Page 564 Chapter 21 Extended EJTAG Interface 21-8...
Page 565: Electrical Characteristics
Chapter 22 Electrical Characteristics 22. Electrical Characteristics (*1) 22.1 Absolute Maximum Rating Parameter Symbol Rating Unit −0.3 ~ 3.9 Supply voltage (for I/O) CCIOMax −0.3 ~ 3.0 Supply voltage (for internal) CCIntMax (*2) −0.3 ~ V + 0.3 Input voltage CCIO −40 ~ +125 °C...
Page 566: Dc Characteristics
Chapter 22 Electrical Characteristics 22.3 DC Characteristics 22.3.1 DC Characteristics Except for PCI Interface = 3.3 V ± 0.3 V, V = 1.5 V ± 0.1 V, V (Tc = 0 ~ 70°C, V = 0 V) CCIO CCInt Parameter Conditions Min.
Page 567: Power Circuit For Pll
Chapter 22 Electrical Characteristics 22.3.2 DC Characteristics Except for PCI Interface = 3.3 V ± 0.3 V, V = 1.5 V ± 0.1 V, V (Tc = 0 ~ 70°C, V = 0 V) CCIO CCInt Parameter Conditions Min. Max. Unit Low-level input voltage -0.5...
Page 568: Ac Characteristics
Chapter 22 Electrical Characteristics 22.5 AC Characteristics 22.5.1 MASTERCLK AC Characteristics = 3.3 V ± 0.3 V, V = 1.5 V ± 0.1 V, V (Tc = 0 ~ 70°C, V = 0 V) CCIO CCInt Parameter Condition Min. Max. Unit ⎯...
Page 569: Sdram Interface Ac Characteristics
Chapter 22 Electrical Characteristics 22.5.3 SDRAM Interface AC Characteristics = 3.3 V ± 0.3 V, V = 1.5 V ± 0.1 V, V (Tc = 0 ~ 70°C, V = 0 V, CL = 50 pF) CCIO CCInt Parameter Symbol Rating Min.
Page 570: External Bus Interface Ac Characteristics
Chapter 22 Electrical Characteristics 22.5.4 External Bus Interface AC Characteristics = 3.3 V ± 0.3 V, V = 1.5 V ± 0.1 V, V (Tc = 0 ~ 70°C, V = 0 V) CCIO CCInt Parameter Symbol Rating Min. Max. Unit ⎯...
Page 571: Pci Interface Ac Characteristics (33 Mhz)
Chapter 22 Electrical Characteristics 22.5.5 PCI Interface AC Characteristics (33 MHz) = 3.3 V ± 0.3 V, V = 1.5 V ± 0.1 V, V (Tc = 0 ~ 70°C, V = 0 V) CCIO CCInt Parameter Symbol Rating Min. Max.
Page 572: Dma Interface Ac Characteristics
Chapter 22 Electrical Characteristics CYCO33 HIGHO33 LOWO33 PCICLK[n] SKEW PCICLK[except for n] n=1∼2 Figure 22.5.7 Timing Diagrams: PCI Clock Skew 22.5.6 DMA Interface AC Characteristics = 3.3 V ± 0.3 V, V = 1.5 V ± 0.1 V, V (Tc = 0 ~ 70°C, V = 0 V) CCIO CCInt...
Page 573 Chapter 22 Electrical Characteristics Note: (1) DMAREQ[n] Edge Detection: Set the pulse width to 1.1× the GBUSCLK cycle or higher. Level Detection: There is no AC characteristic definition. Continue asserting DMAREQ[1:0] until DMAACK[1:0] is received. (2) DMAACK[n] The DMAACK[n] signal is synchronous to SDCLK. (It is driven by GUBSCLK inside the chip. See Chapter 6 for more information.) The DMAACK[n] signal is asserted by SYSCLK or SDCLK for 3 cycles or more.
Page 574: Interrupt Interface Ac Characteristics
Chapter 22 Electrical Characteristics 22.5.7 Interrupt Interface AC Characteristics = 3.3 V ± 0.3 V, V = 1.5 V ± 0.1 V, V (Tc = 0 ~ 70°C, V = 0 V) CCIO CCInt Parameter Symbol Rating Min. Max. Unit 1/2 ×...
Page 575 PIO[31:0] Input Setup time IMBUSCLK Standard SU_PIO ⎯ PIO[31:0] Input Hold time IMBUSCLK Standard HO_PIO Note: The IMBUSCLK is an internal signal. For details, please refer to “Chapter 6 Clocks” in the TMPR4925 Data book. MASTERCLK IMBUSCLK (output) VAL_PIO (input) SU_PIO HO_PIO Figure 22.5.12 Timing Diagrams: PIO Interface...
Page 576: Ac-Link Interface Ac Characteristics
Chapter 22 Electrical Characteristics 22.5.11 AC-link Interface AC Characteristics = 3.3 V ± 0.3 V, V = 1.5 V ± 0.1 V, V (Tc = 0 ~ 70°C, V = 0 V) CCIO CCInt Parameter Symbol Rating Min. Max. Unit BITCLK High time HIGH_BCLK BITCLK Low time...
Page 577: Nand Flash Memory Interface Ac Characteristics
Chapter 22 Electrical Characteristics 22.5.12 NAND Flash Memory Interface AC Characteristics = 3.3 V ± 0.3 V, V = 1.5 V ± 0.1 V, V (Tc = 0 ~ 70°C, V = 0 V) CCIO CCInt Parameter Symbol Rating Min. Max.
Page 578: Chi Interface Ac Characteristics
Chapter 22 Electrical Characteristics 22.5.13 CHI Interface AC Characteristics = 3.3 V ± 0.3 V, V = 1.5 V ± 0.1 V, V (Tc = 0 ~ 70°C, V = 0 V) CCIO CCInt Parameter Symbol Rating Min. Max. Unit ⎯...
Page 579: Spi Interface Ac Characteristics
Chapter 22 Electrical Characteristics 22.5.14 SPI Interface AC Characteristics = 3.3 V ± 0.3 V, V = 1.5 V ± 0.1 V, V (Tc = 0 ~ 70°C, V = 0 V) CCIO CCInt Parameter Symbol Rating Min. Max. Unit ⎯...
Page 580 Chapter 22 Electrical Characteristics 22-16...
Page 581: Pin Layout, Package
Chapter 23 Pin Layout, Package 23. Pin Layout, Package 23.1 Pin Layout Table 23.1.1 shows pin layout, Table 23.1.2 shows pin designations (Coordinates), Table 23.1.3 shows pin designations (Signal name). 23-1...
Page 582 Chapter 23 Pin Layout, Package RAS* SDCS[0]* DQM[1] DQM[0] DATA[15] DATA[29] DATA[28] DATA[27] DATA[26] SDCS[1]* DQM[3] DQM[2] CAS* DATA[31] DATA[30] DATA[13] DATA[12] DATA[11] DATA[10] ADDR[6] ADDR[5] VDDS VDDS DATA[14] VDDC VDDS VDDC VDDC ADDR[8] ADDR[7] ADDR[10] ADDR[9] VDDC VDDS ADDR[13] ADDR[12] ADDR[11] SADDR10 ADDR[14]...
Page 583 Chapter 23 Pin Layout, Package DATA[25] DATA[8] DATA[22] DATA[21] DATA[20] DATA[3] DATA[17] MASTERCLK DATA[9] DATA[23] DATA[6] DATA[5] DATA[4] DATA[18] DATA[1] DATA[0] PLLVDD PLLVSS DATA[24] DATA[7] VDDS VDDC DATA[19] DATA[2] DATA[16] VDDS C32KOUT C32KIN VDDS VDDS TEST* NMI* BC32K PIO[16] PIO[15] PIO[14] PIO[7] PIO[13]...
Page 584 Chapter 23 Pin Layout, Package Table 23.1.2 Pin Designations (Coordinates) PCICLKIO ADDR[16] C_BE[3] PIO[5] VDDC PCIAD[24] VDDC VDDC ADDR[11] PCIAD[25] DATA[5] PIO[13] PIO[26] VDDC VDDS DATA[21] PIO[16] PIO[24] PCIAD[15] TEST* PIO[27] VDDS VDDS C_BE[1] VDDS PIO[22] DQM[2] DATA[12] DATA[0] PIO[19] DQM[1] DATA[28] VDDC...
Page 585 Chapter 23 Pin Layout, Package Table 23.1.3 Pin Designations (Signal name) ACK* DATA[13] PCIAD[17] PLLVSS VDDS ADDR[0] DATA[14] PCIAD[18] PON* VDDS ADDR[1] DATA[15] PCIAD[19] RAS* VDDS ADDR[2] DATA[16] PCIAD[20] REQ[0]* VDDS ADDR[3] DATA[17] PCIAD[21] REQ[1]* VDDS ADDR[4] DATA[18] PCIAD[22] REQ[2]* VDDS ADDR[5] DATA[19]...
Page 586: Package
Chapter 23 Pin Layout, Package 23.2 Package Package Type (Package Code) : 256-pin PBGA / PBGA[4L] (P-BGA256-2727-1.27A4) 23-6...
Page 587: Usage Notes
Chapter 24 Usage Notes 24. Usage Notes 24.1 Limitation on DMA Data Chaining • Overview The DMA Controller works incorrectly if the DMCCRn.IMMCHN bit is cleared and the address increment value (DMSAIRn/DMDAIRn) is negative. The DMA Controller might also work incorrectly regardless of the setting of the DMCCRn.IMMCHN bit if a dynamic or typical DMA chaining is performed after completion of a transfer with a negative address increment.
Page 588 Chapter 24 Usage Notes 24-2...
Page 589: Appendix A. Tx49/H2 Core Supplement
PRId Register values of the TX4925 TX49/H2 Core are as follows. Processor Revision Identifier Register: 0x0000_2D23 FPU Implementation/Revision Register (FCR0): 0x0000_2D21 These values may be changed at a later date. Please contact the Toshiba Engineering Department for the most recent information. Interrupts Interrupt signalling of the on-chip interrupt controller is reflected in bit IP[2] of the Cause Register in the TX49/H2 Core.
Page 590 Appendix A TX49/H2 Core Supplement...

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