Block Diagram - Toshiba TMPR4925 Manual

12.2 Block Diagram

IM-Bus I/F Signal
Counter Input Clock
Timer Interrupt 0
IM-Bus I/F Signal
Counter Input Clock
Timer Interrupt 1
IM-Bus I/F Signal
Counter Input Clock
Timer Interrupt 2
Internal Reset
Chip Configuration
Register (CCFG.WR)
Figure 12.2.1 Connecting Timer Module Inside the TX4925
IM-Bus
Register R/W Control Logic
Reset Signal
Divider
Clock Signal
Interval Timer Mode
Pulse Generator Mode
Interval Timer Mode
Interval Timer Mode
Watchdog Timer Mode
Selector
NMI*
Clock
Clock
x1/2-
Select
1/256
Interval Mode Reg.
Pulse Gen. Mode Reg.
Watchdog Mode Reg.
Timer Control Register
Interrupt Control Register
Figure 12.2.2 Timer Internal Block Diagram
Chapter 12 Timer/Counter
TX4925
Timer-0
Timer-1
Timer-2
Timer
Timer Read Register
Clear
32-bit Counter
Compare Compare
Register A Register B
Comparator (=)
Interrupt
Control Logic
12-2
TIMER[0]
TIMER[1]
TCLK
TIMER[1:0]
Timer Interrupt Request
Signal (Internal Signal)
Watchdog Request Signal
(Internal Signal)