Toshiba TMPR4925 Manual page 583

L M N
DATA[25] DATA[8] DATA[22]
DATA[9] DATA[23] DATA[6]
DATA[24] DATA[7] VDDS
VDDS Vss Vss
Vss VDDS IRDY*
VDDC PCIAD[16] TRDY*
PCIAD[18] C_BE[2] DEVSEL*
PCIAD[17] FRAME* STOP*
P R T
DATA[21] DATA[20] DATA[3]
DATA[5] DATA[4] DATA[18]
VDDC DATA[19] DATA[2]
Vss Vss VDDS
TOP View VDDS
Vss VDDC VDDS
VDDC PAR PCIAD[14] PCIAD[11] VDDS
PERR* C_BE[1] PCIAD[13] PCIAD[10] PCIAD[8]
SERR* PCIAD[15] PCIAD[12] PCIAD[9]
Table 23.1.1 Pin layout (2/2)
23-3
Chapter 23 Pin Layout, Package
U V W
DATA[17] Vss
MASTERCLK
DATA[1] DATA[0] PLLVDD
DATA[16] VDDS C32KOUT C32KIN
Vss TEST* NMI*
Vss PIO[16] PIO[15]
PIO[7] PIO[13] PIO[17]
Vss VDDC PIO[9]
PIO[6] PIO[5] PIO[10]
VDDS PIO[1] PIO[3]
Vss VDDC PIO[4]
PIO[0] PIO[2] CE[1]*
CE[3]* CE[2]* ADDR[15]
VDDS ADDR[2] ADDR[3]
Vss VDDC ADDR[0]
BWE [2]* BWE [3]* UAE
BWE [0]* BWE [1]*
Vss VDDC PCIAD[7]
PCIAD[6]
PCIAD[5]
C_BE[0] PCIAD[4]
Y
Vss 20
PLLVSS 19
18
BC32K 17
PIO[14] 16
PIO[12] 15
PIO[8] 14
PIO[11] 13
ACK* 12
BUSSPRT 11
CE[0]* 10
OE* 9
ADDR[4] 8
ADDR[1] 7
SWE* 6
SYSCLK 5
PCIAD[3] 4
PCIAD[2] 3
PCIAD[1] 2
PCIAD[0] 1