0Xb054 (Ch. 2) 0Xb074 (Ch. 3) - Toshiba TMPR4925 Manual

8.4.8 DMA Destination Address Increment Register (DMDAIRn)
31
Reserved
15
Bits Mnemonic Field Name
⎯
31:24 Reserved
23:0 DADINC Destination
Address
Increment
Figure 8.4.8 DMA Destination Address Increment Register
24 23
DADINC[15:0]
R/W
-
Destination Address Increment (Initial value: undefined, R/W)
This field sets the increase/decrease value of the DMA Destination Address Register
(DMDARn). This value is a 24-bit two's complement and indicates a byte count.
Refer to "8.3.8.1 Channel Register Settings During Dual Address Transfer" for more
information.
8-34
Chapter 8 DMA Controller
0xB014 (ch. 0) 0xB034 (ch. 1)
0xB054 (ch. 2) 0xB074 (ch. 3)
DADINC[23:16]
R/W
-
Description
⎯
16
: Type
: Initial value
0
: Type
: Initial value