Dma/Interrupt Status Register 0 (Sidisr0) 0Xf308 (Ch. 0) Dma/Interrupt Status Register 1 (Sidisr1) 0Xf408 (Ch. 1) - Toshiba TMPR4925 Manual

11.4.3 DMA/Interrupt Status Register 0 (SIDISR0)
DMA/Interrupt Status Register 1 (SIDISR1)
These registers indicate the DMA or interrupt status information.
31
15 14 13 12
UBRK UFER UPER UOER
UVALID
R R R R
0 1 0 0
Bits Mnemonic Field Name
⎯
31:16 Reserved
15 UBRK Receive Break
14 UVALID Receive FIFO
Available Status
13 UFER Frame Error
12 UPER Parity Error
11 UOER Overrun Error
Reception Error
10 ERI
Interrupt
Reception Time
9 TOUT
Out
8 TDIS Transmission
Data Empty
7 RDIS Reception Data
Full
0
11 10 9 8
ERI TOUT TDIS RDIS
R
R/W0C R/W0C R/W0C R/W0C R/W0C
0 0 0 1
UART Break (Initial value: 0, R)
This field indicates the break reception status of the next data in the Receive FIFO to
be read. Reading the Receive FIFO Register (SIRFIFO) updates the status.
0: No breaks
1: Detect breaks
UART Available Data (Initial value: 1, R)
This field indicates whether or not data exists in the Receive FIFO (SIRFIFO).
0: Data exists in the Receive FIFO.
1: No data exists in the Receive FIFO.
UART Frame Error (Initial value: 0, R)
This field indicates the frame error status of the next data in the Receive FIFO to be
read. Reading the Receive FIFO Register (SIRFIFO) updates the status.
0: There are no frame errors.
1: There are frame errors.
UART Parity Error (Initial value: 0, R)
This field indicates the parity error status of the next data in the Receive FIFO to be
read. Reading the Receive FIFO Register (SIRFIFO) updates the status.
0: There are no parity errors.
1: There are parity errors.
UART Overrun Error (Initial value: 0, R)
This register indicates the overrun status of the next data in the Receive FIFO to be
read. Reading the Receive FIFO Register (SIRFIFO) updates the status.
0: There are no overrun errors.
1: There are overrun errors.
Receive Data Error Interrupt (Initial value: 0, R/W0C)
This bit is immediately set to "1" when a reception error (Frame Error, Parity Error, or
Overrun Error) is detected.
Time Out (Initial value: 0, R/W0C)
This bit is set to "1" when a reception time out occurs.
Transmit DMA/Interrupt Status (Initial value: 1, R/W0C)
This bit is set when available space of the amount set by the Transmit FIFO Request
Trigger Level (TDIL) of the FIFO Control Register (SIFCR) exists in the Transmit
FIFO.
Receive DMA/Interrupt Status (Initial value: 0, R/W0C)
This bit is set when valid data of the amount set by the Receive FIFO Request
Trigger Level (RDIL) of the FIFO Control register (SIFCR) is stored in the Receive
FIFO.
Figure 11.4.3 DMA/Interrupt Status Register (1/2)
11-17
Chapter 11 Serial I/O Port
0xF308 (Ch. 0)
0xF408 (Ch. 1)
7 6 5 4
STIS 0
0 0
Description
⎯
16
: Type
: Initial value
0
RFDN
R : Type
00000 : Initial value