Dma Request Control Register (Drqctr) 0Xe024 - Toshiba TMPR4925 Manual

5.2.8 DMA Request Control Register (DRQCTR)
31
15 12
DMAREQ[3]
R/W
0x0
Bits Mnemonic Field Name
⎯
31:16 Reserved
15:12 DMAREQ[3] DMA Request 3
11:8 DMAREQ[2] DMA Request 2
7:4 DMAREQ[1] DMA Request 1
3:0 DMAREQ[0] DMA Request 0
Figure 5.2.8 DMA Request Control Register (DRQCTR)
Reserved
11 8 7
DMAREQ[2]
R/W
0x0
DMA Request 3 (Initial value: 0x0, R/W)
This field selects the DMA request source of DMAREQ[3].
0xxx: reserved
1000: SIO ch0. Receive
1001: SIO ch1 Receive
1010: SIO ch0. Transmit
1011: SIO ch1 Transmit
1100: ACLC ch0
1101: ACLC ch1
1110: ACLC ch2
1111: ACLC ch3
DMA Request 2 (Initial value: 0x0, R/W)
This field selects the DMA request source of DMAREQ[2].
0xxx: reserved
1000: SIO ch0. Receive
1001: SIO ch1 Receive
1010: SIO ch0. Transmit
1011: SIO ch1 Transmit
1100: ACLC ch0
1101: ACLC ch1
1110: ACLC ch2
1111: ACLC ch3
DMA Request 1 (Initial value: 0x0, R/W)
This field selects the DMA request source of DMAREQ[1].
0xxx: DMAREQ[1] (external signal)
1000: SIO ch0. Receive
1001: SIO ch1 Receive
1010: SIO ch0. Transmit
1011: SIO ch1 Transmit
1100: ACLC ch0
1101: ACLC ch1
1110: ACLC ch2
1111: ACLC ch3
DMA Request 0 (Initial value: 0x0, R/W)
This field selects the DMA request source of DMAREQ[0].
0xxx: DMAREQ[0] (external signal)
1000: SIO ch0. Receive
1001: SIO ch1 Receive
1010: SIO ch0. Transmit
1011: SIO ch1 Transmit
1100: ACLC ch0
1101: ACLC ch1
1110: ACLC ch2
1111: ACLC ch3
5-11
Chapter 5 Configuration Register
0xE024
4 3
DMAREQ[1]
R/W
0x0
Description
⎯
16
: Type
: Initial value
0
DMAREQ[0]
R/W : Type
0x0 : Initial value