Nand Flash Memory Interrupt Mask Register (Ndfimr) 0Xc010 - Toshiba TMPR4925 Manual

18.4.5 NAND Flash Memory Interrupt Mask Register (NDFIMR)
31
15
Reserved
Bits Mnemonic Field Name
⎯
31:8 Reserved
7 INTEN Interrupt Enable
⎯
6:1 Reserved
0 MRDY Mask RDY
interrupt
Figure 18.4.5 NAND Flash Memory Interrupt Mask Register (NDFIMR)
Chapter 18 NAND Flash Memory Controller
Reserved
8 7 6
INTEN
R/W
0
Interrupt Enable (Initial value: 0, R/W)
Enable Interrupt. When this bit and MRDY bit in this register are set one and RDY
bit in NDFISR becomes one, the interrupt occurs.
0: Disable
1: Enable
Mask Ready Interrupt (Initial value: 0, R/W)
This bit masks the RDY bit in NDFISR. If this bit one, RDY in NDFISR set when
ND_RB* signal changes from Low to High.
0: Disable RDY in NDFISR
1: Enable RDY in NDFISR
18-9
0xC010
1
Reserved
Description
⎯
⎯
16
: Type
: Initial value
0
MRDY
R/W : Type
0 : Initial value