Transmit Fifo Register 0 (Sitfifo0) 0Xf31C (Ch. 0) Transmit Fifo Register 1 (Sitfifo1) 0Xf41C (Ch. 1) - Toshiba TMPR4925 Manual

11.4.8 Transmit FIFO Register 0 (SITFIFO0) 0xF31C (Ch. 0)
Transmit FIFO Register 1 (SITFIFO1) 0xF41C (Ch. 1)
When using the DMA Controller to perform DMA transmission, set the following addresses in the
Destination Address Register (DMDARn) of the DMA Controller according to the Endian Mode bit
(DMCCRn.LE) setting of the DMA Controller.
•
Little Endian:
•
Big Endian:
31
15
0
Bits Mnemonic Field Name
⎯
31:8 Reserved
Transmission
7:0 TxD
Data
0xF31C (Ch.0), 0xF41C (Ch.1)
0xF31F (Ch.0), 0xF41F (Ch.1)
0
8 7
Transmit Data (Initial value: –, W)
Data written to this register are written to the Transmit FIFO.
Figure 11.4.8 Transmit FIFO Register
11-23
Chapter 11 Serial I/O Port
TxD
W
⎯
Description
⎯
16
: Type
: Initial value
0
: Type
: Initial value