Toshiba TMPR4925 Manual page 125

Chapter 7 External Bus Controller
SYSCLK
CE*
ADDR [19:0]
OE*
DATA [31:0]
ACK*/READY (Input)
2 clocks 2
clocks
Latch
Latch
Acknowledge
Acknowledge
Data
Data
ACK*
ACK*
EBCCRn.SHWT=0
Figure 7.3.12 ACK* Input Timing (Burst Read Cycle)
SYSCLK
CE*
ADDR [19:0]
3 clocks 3 clocks
SWE*/BWE*
4 clocks 4 clocks
DATA [31:0]
ACK*/READY (Input)
Acknowledge ACK*
Acknowledge ACK*
EBCCRn.SHWT=0
Figure 7.3.13 ACK* Input Timing (Burst Write Cycle)
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