Pci Boot - Toshiba TMPR4925 Manual

10.3.11.3 Bus Parking
The On-chip PCI Bus Arbiter supports bus parking.
The last PCI Bus Master is made the Park Master when the Fix Park Master bit (FIXPM) of the
PCI Bus Arbiter Configuration Register (PBACFG) is cleared (in the default state). When this bit
is set, the Internal PCI Bus Arbiter Request A Port (Master A) becomes the Park Master.
10.3.11.4 Broken Master Detect
The TX4925 On-chip PCI Bus Arbiter has a function for automatically detecting broken
masters.
If the PCI Bus Master requests and is granted the bus when the PCI Bus is in the Idle state, this
master must assert the FRAME* signal within 16 PCI Clock cycles and start a transaction. The
PCI Bus Arbiter recognizes any device that breaks this rule as a broken bus master and removes
that device from the bus arbitration sequence.
This detection function is enabled when the Broken Master Check Enable bit (BMCEN) of the
PCI Bus Arbiter Configuration Register (PBACFG) is set. When a broken master is detected, the
Broken Master Detection bit (PBSTATUS.BMD) of the PCI Bus Arbiter Status Register is set and
the bit in the PCI Bus Arbiter Broken Master Register (PBABM) that corresponds to that master is
set. Then it also becomes possible to report an interrupt.

10.3.12 PCI Boot

Setting the configuration during boot up (ADDR[8:6] = 0x011) makes it possible to set the reset
exception vector address of the TX49/H2 core to PCI Bus address 0xBFC0_0000.
Two windows of the memory space from the G-Bus to the PCI Bus space are used when in the PCI
Boot mode. The defaults of several registers are changed as indicated below.
•
G-Bus base address (G2GBASE):
•
Space size (G2PM2MASK):
•
PCI Bus base address (G2PM2PBASE):
•
Initiator Memory Space 2 Enable (PCICCFG.G2PM2EN):
•
Bus Master bit (PCISTATUS.BM) [Only when in the Host mode]
•
Target Configuration Access Ready
(PCICSTAUTS.TCAR) [Only when in the Satellite mode]
Also, the on-chip PCI Bus Arbiter cannot be used when the PCI Boot mode is being used while in the
Satellite mode.
Chapter 10 PCI Controller
10-22
0x1FC0_0000
4 MB
0xBFC0_0000
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