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At the end of every series of transmission the software is supposed to negate the chip select signal for
the target device by the following procedure.
(1) Check if SRRDY or RBSI is a logic "1". If not, do nothing.
(2) Check if SIDLE is a logic "1". If not, do nothing.
(3) Negate the chip select signal.
The SPI supports either 8-bit per character or 16-bit per character operation, as defined by the SSZ
bits in the SPI Control Register 1 (SPCR1). The software can also select whether the MSB or LSB
should shift first using the SBOS bit in the SPI Control Register 0 (SPCR0). Another set of SPHA and
SPOL bits bit in the SPI Control Register 0 (SPCR0) select the transfer format. Please see to "17.3.4
Transfer Format".
17.3.3
Baud Rate Generator
The rate of the SPICLK signal is determined by the value of the SER[7:0] bits in the SPI Control
Register 1 (SPCR1). The SER[7:0] bits are used by the Baud Rate Generator to devide the SPI master
clock generated by the Clock Generator (CG). The frequency of the SPI master clock is 40 MHz when
MASTERCLK input is 80 MHz. The SPICLK rate is shown in the table below in this time.
Table 17.3.1 SPICLK Rate when MASTERCLK is 80 MHz
Chapter 17 Serial Peripheral Interface
SER[7:0]
SPI Clock Rate
00000001b
10 MHz
00000010b
6.667 MHz
00000011b
5 MHz
00000100b
4 MHz
00000101b
3.33 MHz
...
00001001b
2 MHz
...
00010011b
1 MHz
...
11111111b
78.125 KHz
17-4
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