Bus Errors; Memory Read And Memory Write; Slow Write Burst - Toshiba TMPR4925 Manual

9.3.4.2 Advanced CKE
Advanced CKE is a function that speeds up the CKE assertion and deassertion timing by 1
clock cycle. This function is set using the Address CKE bit (SDCTR.ACE) of the SDRAM Timing
Register.
Advanced CKE assumes that it will be used in a system where SDRAM data is saved even
when the power to the TX4925 itself is cut. Since CKE On/Off becomes 1 cycle faster, it is
possible to delay CKE by 1 clock cycle using external power consumption control logic. Please set
the SDRAM to the Self-Refresh mode before using this function.
When combining advanced CKE functionality with Power Down Auto Entry functionality and
memory access is requested while in the Power Down mode, two more SDCLK cycles of latency
are added than would be the case when not in the Power Down mode.
9.3.5

Bus Errors

The SDRAMC detects bus errors in the following situations:
•
Bus time-out occurs during Read or Write operation to the SDRAMC
If a bus error occurs when accessing the SDRAMC, then the SDRAMC will immediately abort
current operation. Then, the current SDRAM cycle will end, remaining SDRAMC operations will be
aborted, a Pre-charge All command will be issued to SDRAM, then the SDRAMC will return to the Idle
state.
9.3.6

Memory Read and Memory Write

The RAS* signal, CAS* signal, WE*, signal, ADDR[19:16], SADDR10, and ADDR[14:5] signal are
set up 1 cycle before the SDCS* signal is asserted in the case of the Read command, Write command,
Pre-charge command, or Mode Register Set command. The same set up time is observed even for active
commands if the Active Command Ready bit (SDCTR.DA) of the SDRAM Timing Register is set.
Figure 9.5.1 is a timing diagram of Single Read operation when the SDCTR.DA bit is cleared. Figure
9.5.2 is a timing diagram of Single Read operation when the SDCTR.DA bit is set.
Burst or Single Read operation is terminated by the Pre-charge Active Bank command. Burst or
Single Write operation is terminated by the Auto Pre-charge Command.
9.3.7

Slow Write Burst

When the Slow Write Burst bit (SDCTR.SWB) of the SDRAM Timing Register is cleared, the data
changes at each cycle during Burst Write operation (Figure 9.5.6). When the Slow Write Burst bit is set,
the data will change every other cycle (Figure 9.5.7).
When Slow Write Burst bit is set, it always operates as t
relation with the value of RAS-CAS Delay bit (SDCTR.RCD) of SDRAM Timing Register. When slow
write burst is invalid, the value of RAS-CAS Delay bit is valid. During read access the value of RAS-
CAS Delay bit is valid in no relation with Slow Write Burst bit setup.
Chapter 9 SDRAM Controller
= 3t
RCD
9-11
against all write access in no
CK