Clocks; Tx4925 Clock Signals - Toshiba TMPR4925 Manual

6.

Clocks

6.1

TX4925 Clock Signals

Figure 6.1.1 shows the configuration of TX4925 blocks and clock signals. Table 6.1.1 describes each clock
signal. Table 6.1.2 shows the relationship among different clock signals when the CPU clock frequency is
200 MHz.
CG
PLL
x2.5
MASTERCLK
OSC x4
PDNCTR.STPCPU
TMR2CKE
TMR1CKE
TMR0CKE
C32IN
OSC
C32OUT
TX4925
1/6
1/1
1/2
1/3
1/4
ADDR[4:3]
1/1
1/2
CPUCLK
1/4
1/8
1/1
1/2
GBUSCLK
1/4
1/8
1/2
CCFG.RF
GBUSCLKF
IMBUSCLKF
1/2
DMACKE
PCICKE
CHICKE
PIOCKE
SIO1CKE
SIO0CKE
ACLCKE
SPICKE
CLKCTR
Figure 6.1.1 TX4925 Block and Clock Configuration
Chapter 6 Clocks
TX49/H2 Core
EJTAG/DSU
SDCLK[1:0]
DATA latch
SDRAMC
Refresh Counter
EBUSC
NDFMC
CLKGATE
DMAC
PCIC
CHI
IRC
CLKGATE
PIO
TMR2
TMR1
TMR0
SIO1
SIO0
ACLC
SPI
RTC
6-1
PCICLK[2:1]
PCI
PCICLK_IO
SYSCLK
External Device
TCK
DCLK
SDRAM
SDCLKIN
CHICLK
TCLK
SCLK
BITCLK
BC32K