G2P Configuration Register (G2Pcfg) 0Xd060 - Toshiba TMPR4925 Manual

64-bit tx system risc tx49 family
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10.4.13 G2P Configuration Register (G2PCFG)
31
15
12
Reserved
BSWAPM0 BSWAPM1 BSWAPM2 BSWAPIO G2PM0EN G2PM1EN G2PM2EN
R/W
0/1
Bits
Mnemonic
Field Name
31:12
Reserved
Byte Swap for
11
BSWAPM0
Memory Space 0
Byte Swap for
10
BSWAPM1
Memory Space 1
Byte Swap for
9
BSWAPM2
Memory Space 2
8
BSWAPIO
Byte Swap for I/O
Space
7
G2PM0EN
Initiator Memory
Space 0 Enable
Initiator Memory
6
G2PM1EN
Space 1 Enable
Reserved
11
10
9
8
R/W
R/W
R/W
R/W
0/1
0/1
0/1
Byte Swap Disable for Memory Space 0
(Initial value: Little Endian Mode: 0; Big Endian Mode: 1, R/W)
Sets the byte swapping of Memory Space 0.
0: Do not perform byte swapping.
1: Perform byte swapping.
Please use the default state in most situations. If this bit is changed to "0" when in the
Big Endian Mode, the byte order of transfer to Memory Space 0 through DWORD (32-
bit) access will not change.
Byte Swap Disable for Memory Space 1
(Initial value: Little Endian Mode: 0; Big Endian Mode: 1, R/W)
Sets the byte swapping of Memory Space 1.
0: Do not perform byte swapping.
1: Perform byte swapping.
Please use the default state in most situations. If this bit is changed to "0" when in the
Big Endian Mode, the byte order of transfer to Memory Space 1 through DWORD (32-
bit) access will not change.
Byte Swap Disable for Memory Space 2
(Initial value: Little Endian Mode: 0; Big Endian Mode: 1, R/W)
Sets the byte swapping of Memory Space 2.
0: Do not perform byte swapping.
1: Perform byte swapping.
Please use the default state in most situations. If this bit is changed to "0" when in the
Big Endian Mode, the byte order of transfer to Memory Space 2 through DWORD (32-
bit) access will not change.
Byte Swap Disable for I/O Space
(Initial value: Little Endian Mode: 0; Big Endian Mode: 1, R/W)
Sets the byte swapping of I/O Space.
0: Do not perform byte swapping.
1: Perform byte swapping.
Please use the default state in most situations. If this bit is changed to "0" when in the
Big Endian Mode, the byte order of transfer to I/O Space through DWORD (32-bit)
access will not change.
Initiator Memory Space 0 Enable (Initial value: 0, R/W)
Controls PCI initiator access to Memory Space 0.
1: Memory Space 0 is valid.
0: Memory Space 0 is invalid.
Initiator Memory Space 1 Enable (Initial value: 0, R/W)
Controls PCI initiator access to Memory Space 1.
1: Memory Space 1 is valid.
0: Memory Space 1 is invalid.
Figure 10.4.13 G2P Configuration Register (1/2)
10-39
Chapter 10 PCI Controller
0xD060
7
6
5
4
IRBER
G2PIOEN
R/W
R/W
R/W
R/W
0
0
0
0
Description
16
: Type
: Initial value
3
2
1
0
ASERR
Reserved BSWAPI
R/W R/W1C : Type
1
0/1
0
: Initial value

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