Chi Rx Holding Register (Chihold) 0Xa824 - Toshiba TMPR4925 Manual

16.4.11 CHI RX Holding Register (CHIHOLD)
31
15
Bits Mnemonic Field Name
31:0 CHIHOLD[31:0] CHIRXHOLD
CHIRXHOLD
R
0000000000000000
CHIRXHOLD
R
0000000000000000
CHIRXHOLD bits (Initial value: 32'b0, R)
These bits represent the CHI data to be received. CHI data can be either read
directly from this register by the CPU or transparently written to the CHI RX DMA
buffer from this register. This register should only be read by the CPU after the
CHIININTA or CHIININTB interrupt is asserted. The read immediately after
CHIININTA sees the internal RX holding register A and the read immediately after
CHIININTB sees the internal RX holding register B. Receive data for bytes 3, 2, 1,
and 0 are stored into the 32-bit CHIRXHOLD at locations [31:24], [23:16], [15:8],
and [7:0], respectively. These data bytes correspond to the CHI timeslots as defined
by the values in the RXPTRA and RXPTRB TDM switch registers.
Figure 16.4.11 CHI RX Holding Register (CHIHOLD)
16-31
Chapter 16 CHI Module
0xA824
Description
16
: Type
: Initial value
0
: Type
: Initial value