Table of Contents
Advertisement
MICRO-ARCHITECTURE OVERVIEW
back mechanism and a pseudo-LRU replacement algorithm. The data cache consists of eight
banks interleaved on four-byte boundaries.
On the Pentium II processors, the data cache can be accessed simultaneously by a load
instruction and a store instruction, as long as the references are to different cache banks. On
Pentium II processors the minimum delay is ten internal clock cycles.
2.4.
WRITE BUFFERS
Processors with MMX technology have four write buffers (versus two in Pentium processors
without MMX technology). Additionally, the write buffers can be used by either pipe (versus
one corresponding to each pipe in Pentium processors without MMX technology).
Performance of critical loops can be improved by scheduling the writes to memory; when
you expect to see write misses, you should schedule the write instructions in groups no larger
than four, then schedule other instructions before scheduling further write instructions.
2.5.
ADDITIONAL INFORMATION
For more information on how to program with MMX Technology, see the MMX™
Technology Developer's Guide on the Intel web site at http://developer.intel.com.
2.6.
ARCHITECTURE SUMMARY
Dynamic Execution is the combination of improved branch prediction, speculative execution
and data flow analysis that enable P6 family processors to deliver superior performance. The
addition of MMX technology makes the Pentium II processor the fastest processor in the
Intel family of processors.
2-14
Advertisement
Table of Contents
