Non-Burst, Non-Pipelined Read Request With Wait States - Intel 80960HA Datasheet

80960HA/HD/HT
Figure 33. Non-Burst, Non-Pipelined Read Request with Wait States
PMCON
A31:2, BE3:0
LOCK, CT3:0
58
External
Pipe-
Ready
Function
Burst
Lining
Control
Bit
29 28 24
Disabled
OFF
Disabled
Value
0 0
0
NOTE:
Bits 31-30, 27-25, 13, and 5 are reserved.
A
CLKIN
ADS
W/R
BLAST
DT/R
DEN
D/C, SUP,
WAIT
D31:0,
DP3:0
PCHK
Bus Parity
Odd
N
Parity Enable
Width XDA
23-22 21 20 19-16
X
X Enabled 1
x 1
xx 0001
3
2 1
Valid
Valid
N
N N N
RAD
RDD
WDD WAD
15-14 12-8 7-6 4-0
X X
3
X
xx xxxxx
00011
xx
D 1
A
In
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