2. Design Example Detailed Description
710496 | 2022.01.28
Software
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Intel Quartus Prime software version 21.4 Patch 0.01
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Either one of the following simulators for functional simulation:
— ModelSim - Intel FPGA Edition
— Questa-Intel FPGA Edition
— VCS/VCS MX
— Xcelium (Verilog only)
Related Information
Why does the SDI II Intel
the Support-Logic Generation stage?
2.3. Functional Description
The SDI II Intel FPGA IP core design example supports the following simplex and
duplex transceiver mode:.
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Parallel loopback with simplex mode
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Parallel loopback with duplex mode
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Serial loopback with simplex mode
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Serial loopback with duplex mode
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F-Tile FPGA IP design example fail to compile at
F-Tile SDI II Intel
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FPGA IP Design Example User Guide
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