ST STM32F207 Series Reference Manual page 1244

USB on-the-go high-speed (OTG_HS)
Application programming sequence:
1. Asserting the IISOOXFRM interrupt (OTG_HS_GINTSTS) indicates that in the current
frame, at least one isochronous OUT endpoint has an incomplete transfer.
2. If this occurs because isochronous OUT data is not completely emptied from the
endpoint, the application must ensure that the application empties all isochronous OUT
data (data and status) from the receive FIFO before proceeding.
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3. When it receives an IISOOXFRM interrupt (in OTG_HS_GINTSTS), the application
must read the control registers of all isochronous OUT endpoints
(OTG_HS_DOEPCTLx) to determine which endpoints had an incomplete transfer in
the current micro-frame. An endpoint transfer is incomplete if both the following
conditions are met:
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4. The previous step must be performed before the SOF interrupt (in
OTG_HS_GINTSTS) is detected, to ensure that the current frame number is not
changed.
5. For isochronous OUT endpoints with incomplete transfers, the application must discard
the data in the memory and disable the endpoint by setting the EPDIS bit in
OTG_HS_DOEPCTLx.
6. Wait for the EPDIS interrupt (in OTG_HS_DOEPINTx) and enable the endpoint to
receive new data in the next frame.
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Stalling a nonisochronous OUT endpoint
This section describes how the application can stall a nonisochronous endpoint.
1. Put the core in the Global OUT NAK mode.
2. Disable the required endpoint
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3. When the application is ready to end the STALL handshake for the endpoint, the
STALL bit (in OTG_HS_DOEPCTLx) must be cleared.
4. If the application is setting or clearing a STALL for an endpoint due to a
SetFeature.Endpoint Halt or ClearFeature.Endpoint Halt command, the STALL bit must
be set or cleared before the application sets up the Status stage transfer on the control
endpoint.
Examples
This section describes and depicts some fundamental transfer types and scenarios.
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Slave mode bulk OUT transaction
Figure 391
and describes the events involved in the process.
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When all data are emptied from the receive FIFO, the application can detect the
XFRC interrupt (OTG_HS_DOEPINTx). In this case, the application must re-
enable the endpoint to receive isochronous OUT data in the next frame.
EONUM bit (in OTG_HS_DOEPCTLx) = SOFFN[0] (in OTG_HS_DSTS)
EPENA = 1 (in OTG_HS_DOEPCTLx)
Because the core can take some time to disable the endpoint, the application may
not be able to receive the data in the next frame after receiving bad isochronous
data.
When disabling the endpoint, instead of setting the SNAK bit in
OTG_HS_DOEPCTL, set STALL = 1 (in OTG_HS_DOEPCTL).
The STALL bit always takes precedence over the NAK bit.
depicts the reception of a single Bulk OUT Data packet from the USB to the AHB
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