ST STM32F207 Series Reference Manual page 1365

RM0033
Date
05-Nov-2012
Table 224. Document revision history (continued)
Version
I2C:
Modified Section 23.3.7: DMA
Updated definition of PE and note related to SWRST bit, moved note
related to STOP bit to the whole register in
Control register 1 (I2C_CR1)
Updated bit 14 description in
register 1 (I2C_OAR1).
CAN:
Updated dual CAN block diagram.
Updated register description and definition of CAN2SB bits in
Section : CAN filter master register
ETHERNET:
RTPR renamed PM in
Updated value of HCLK for CR= 001 in
address register
USB OTG FS:
Updated remote wakeup signaling bit and the resume interrupt in
Section : Suspended
USB OTG HS:
5
Renamed PHYSEL into PHSEL and changed from bit 7 to bit 6 of the
(continued)
OTG_HS_GUSBCFG register. Updated remote wakeup signaling bit
and the resume interrupt in
OTG_HS_DIEPEACHMSK1and OTG_HS_DOEPEACHMSK1
address offsets and reset values.
FSMC:
Updated step b) in
transactions.
Updated case of synchronous accesses in
Flash/PSRAM controller asynchronous
caution note in
Changed data_setup_phase and data_phase to DATAST in
WAIT management in asynchronous
Section 31.5.3: General timing rules/Signals
Updated step3 of
Figure 418: Access to non 'CE don't care' NAND-Flash
below. Updated access to I/O Space in
Card/CompactFlash
and Table 204: 16-bit PC-Card signals and access
Updated BUSTURN bit definition in
chip-select control registers 1..4
to 19 to BUSTURN in
registers 1..4
Changed min. value for address set to 0 in
Table 178,
RM0033 Rev 9
Changes
requests.
Section 23.6.3: I
Table 145: Source address
(ETH_MACMIIAR).
state.
Section : Suspended state
Section 31.3.1: Supported memories and
Section 31.6.1: External memory interface
Section 31.6.4: NAND Flash
operations. Updated
(FSMC_BCR1..4). Changed bits 16
Section : SRAM/NOR-Flash chip-select timing
(FSMC_BTR1..4).
Table 180, and Table 181.
Revision history
Section 23.6.1: I
2
C Own address
(CAN_FMR).
filtering.
Section : Ethernet MAC MII
.
Updated
Section 31.5.4: NOR
transactions. Removed
signals.
accesses. Updated
synchronization.
operations, updated
and note
Section 31.6.7: PC
Table 202: 16-bit PC Card
type.
Section : SRAM/NOR-Flash
Table 175, Table
1365/1381
2
C
Section :
177,
1375