ST STM32F207 Series Reference Manual page 1296

Flexible static memory controller (FSMC)
Bit 7 Reserved, must be kept at reset value.
Bit 6 FACCEN: Flash access enable
Bits 5:4 MWID[1:0]: Memory databus width.
Bits 3:2 MTYP[1:0]: Memory type.
Bit 1 MUXEN: Address/data multiplexing enable bit.
Bit 0 MBKEN: Memory bank enable bit.
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Enables NOR Flash memory access operations.
0: Corresponding NOR Flash memory access is disabled
1: Corresponding NOR Flash memory access is enabled (default after reset)
Defines the external memory device width, valid for all type of memories.
00: 8 bits,
01: 16 bits (default after reset),
10: reserved, do not use,
11: reserved, do not use.
Defines the type of external memory attached to the corresponding memory bank:
00: SRAM (default after reset for Bank 2...4)
01: PSRAM (CRAM)
10: NOR Flash/OneNAND Flash (default after reset for Bank 1)
11: reserved
When this bit is set, the address and data values are multiplexed on the databus, valid
only with NOR and PSRAM memories:
0: Address/Data nonmultiplexed
1: Address/Data multiplexed on databus (default after reset)
Enables the memory bank. After reset Bank1 is enabled, all others are disabled.
Accessing a disabled bank causes an ERROR on AHB bus.
0: Corresponding memory bank is disabled
1: Corresponding memory bank is enabled
RM0033 Rev 9
RM0033