ST STM32F207 Series Reference Manual page 1320

Debug support (DBG)
Note: The debug features embedded in the Cortex
Design Kit.
The Arm
•
SWJ-DP: Serial wire / JTAG debug port
•
AHP-AP: AHB access
•
ITM: Instrumentation trace macrocell
•
FPB: Flash patch breakpoint
•
DWT: Data watchpoint trigger
•
TPUI: Trace port unit interface (available on larger packages, where the corresponding
pins are mapped)
•
ETM: Embedded Trace Macrocell (available on larger packages, where the
corresponding pins are mapped)
It also includes debug features dedicated to the STM32F20x and STM32F21x:
•
Flexible debug pinout assignment
•
MCU debug box (support for low-power modes, control over peripheral clocks, etc.)
Note: For further information on debug functionality supported by the Arm
to the Cortex
TRM (see
32.2 Reference Arm
•
Cortex
(see Related documents on page 1)
•
Arm
•
Arm
32.3 SWJ debug port (serial wire and JTAG)
The core of the STM32F20x and STM32F21x integrates the Serial Wire / JTAG Debug Port
(SWJ-DP). It is an Arm
interface and a SW-DP (2-pin) interface.
•
The JTAG Debug Port (JTAG-DP) provides a 5-pin standard JTAG interface to the
AHP-AP port.
• The Serial Wire Debug Port (SW-DP) provides a 2-pin (clock + data) interface to the
AHP-AP port.
In the SWJ-DP, the two JTAG pins of the SW-DP are multiplexed with some of the five JTAG
pins of the JTAG-DP.
1320/1381
® ®
Cortex -M3 core provides integrated on-chip debug support. It is comprised of:
ort
p
®
-M3 -r2p0 Technical Reference Manual and to the CoreSight Design Kit-r2p0
Section 32.2).
®
documentation
®
-M3 r2p0 Technical Reference Manual (TRM)
®
Debug Interface V5
®
CoreSight Design Kit revision r2p0 Technical Reference Manual
®
standard CoreSight debug port that combines a JTAG-DP (5-pin)
®
-M3 core are a subset of the Arm
RM0033 Rev 9
RM0033
®
CoreSight
® ®
Cortex -M3 core, refer