ST STM32F207 Series Reference Manual page 1374

Revision history
Date
25-Feb-2021
1374/1381
Table 224. Document revision history (continued)
Version
Updated:
– Section 5: Reset and clock control
Section 5.3.2: RCC PLL configuration register (RCC_PLLCFGR)
– Section 9: DMA controller
Table 22: DMA1 request mapping
Table 23: DMA2 request mapping
– Section 10: Analog-to-digital converter
Section 10.8.1: Using the DMA
Section : Dual ADC mode
Section 10.10: Temperature sensor
– Section 13: Advanced-control timers (TIM1 and
Figure 65: Advanced-control timer block diagram
Figure 92: Capture/compare channel 1 main circuit
Section 13.4.9: TIM1 and TIM8 capture/compare enable register
(TIMx_CCER)
9
– Section 14: General-purpose timers (TIM2 to
Figure 139: Capture/compare channel 1 main circuit
– Section 23: Inter-integrated circuit (I2C)
Section 23.6.8: I
– Section 24: Universal synchronous asynchronous receiver
transmitter
Figure 227: Start bit detection when oversampling by 16 or 8
– Section 25: Serial peripheral interface
Figure 248: SPI block diagram
– Section 26: Secure digital input/output interface
Section 26.9.2: SDI clock control register (SDIO_CLKCR)
– Section 27: Controller area network
Section 27.4.1: Initialization mode
RM0033 Rev 9
Changes
(DMA):
2
C Clock control register (I2C_CCR)
(USART):
RM0033
(RCC):
(ADC):
TIM8):
TIM5):
interface:
(SPI):
(SDIO):
(bxCAN):