ST STM32F207 Series Reference Manual page 1129

RM0033
OTG_HS USB configuration register (OTG_HS_GUSBCFG)
Address offset: 0x00C
Reset value: 0x0000 1440
This register can be used to configure the core after power-on or a changing to host mode
or peripheral mode. It contains USB and USB-PHY related configuration parameters. The
application must program this register before starting any transactions on either the AHB or
the USB. Do not make changes to this register after the initial programming.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Reserved
rw rw rw rw rw rw rw rw rw rw rw rw
Bit 31 CTXPKT: Corrupt Tx packet
This bit is for debug purposes only. Never set this bit to 1.
Note: Accessible in both peripheral and host modes.
Bit 30 FDMOD: Forced peripheral mode
Writing a 1 to this bit forces the core to peripheral mode irrespective of the OTG_HS_ID input
pin.
0: Normal mode
1: Forced peripheral mode
After setting the force bit, the application must wait at least 25 ms before the change takes
effect.
Note: Accessible in both peripheral and host modes.
Bit 29 FHMOD: Forced host mode
Writing a 1 to this bit forces the core to host mode irrespective of the OTG_HS_ID input pin.
0: Normal mode
1: Forced host mode
After setting the force bit, the application must wait at least 25 ms before the change takes
effect.
Note: Accessible in both peripheral and host modes.
Bits 28:26 Reserved, must be kept at reset value.
Bit 25 ULPIIPD: ULPI interface protect disable
This bit controls the circuitry built in the PHY to protect the ULPI interface when the link tri-
states stp and data. Any pull-up or pull-down resistors employed by this feature can be
disabled. Please refer to the ULPI specification for more details.
0: Enables the interface protection circuit
1: Disables the interface protection circuit
Bit 24 PTCI: Indicator pass through
This bit controls whether the complement output is qualified with the internal V
comparator before being used in the V
specification for more details.
0: Complement Output signal is qualified with the Internal V
1: Complement Output signal is not qualified with the Internal V
USB on-the-go high-speed (OTG_HS)
TRDT
rw rw
state in the RX CMD. Please refer to the ULPI
BUS
RM0033 Rev 9
9 8 7 6 5 4 3
Reserved
rw rw rw
BUS
valid comparator
BUS
valid comparator
BUS
2 1 0
TOCAL
rw
valid
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