ST STM32F207 Series Reference Manual page 1371

RM0033
Date
26-Apr-2018
Table 224. Document revision history (continued)
Version
TIM9 to 14
Updated Section 15.4.3: TIM9/12 slave mode control register
(TIMx_SMCR)
bits[2:0] for the slave timer clock.
Updated TIMx_SMCR and TIMx_CCMR1 register adding
"consecutive" in the description.
Updated Section 15.4.10: TIM9/12 prescaler
Added OPM bit in
(TIMx_CR1)
Changed TIMx_ARR reset value to 0xFFFF.
TIM6 and TIM7
Updated Section 16.4.7: TIM6 and TIM7 prescaler (TIMx_PSC)
Changed TIMx_ARR reset value to 0xFFFF.
WWDG
Figure 193: Watchdog block diagram
7-bit. downcounter..
HASH
HASH availability restricted to STM32F21xx devices.
RTC
8
(continued)
Updated WUCKSEL prescaler input in
diagram.
Updated 3rd step in
Updated Section 22.3.7: Resetting the
Updated Section 22.3.8: RTC reference clock
Added note for WUFE bit in
(RTC_CR).
Updated WUTWF bit definition in
and status register
I2C
Updated FREQ[5:0] description in
register 2 (I2C_CR2)
USART
Replaced all occurrences of
– nCTS by CTS
– nRTS by RTS
– SCLK by CK
Removed note related to RXNEIE in
Added note in ONEBIT description in
3 (USART_CR3).
RM0033 Rev 9
Changes
encoder mode description and adding note on
Section 15.5.1: TIM10/11/13/14 control register 1
replacing 6-bit downcounter by
Figure 215: RTC block
Section : Programming the wakeup
RTC.
Section 22.6.3: RTC control register
Section 22.6.4: RTC initialization
(RTC_ISR).
Section 23.6.2: I
to make it generic for all products.
Section : Reception using
Section 24.6.6: Control register
Revision history
(TIMx_PSC).
timer.
detection.
2
C Control
DMA.
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