ST STM32F207 Series Reference Manual page 1106

USB on-the-go high-speed (OTG_HS)
Endpoint controls
The following endpoint controls are available through the device endpoint-x IN/OUT control
register (DIEPCTLx/DOEPCTLx):
•
Endpoint enable/disable
•
Endpoint activation in current configuration
•
Program the USB transfer type (isochronous, bulk, interrupt)
•
Program the supported packet size
•
Program the Tx-FIFO number associated with the IN endpoint
•
Program the expected or transmitted data0/data1 PID (bulk/interrupt only)
•
Program the even/odd frame during which the transaction is received or transmitted
(isochronous only)
• Optionally program the NAK bit to always send a negative acknowledge to the host
regardless of the FIFO status
•
Optionally program the STALL bit to always stall host tokens to that endpoint
•
Optionally program the Snoop mode for OUT endpoint where the received data CRC is
not checked
Endpoint transfer
The device endpoint-x transfer size registers (DIEPTSIZx/DOEPTSIZx) allow the application
to program the transfer size parameters and read the transfer status.
The programming operation must be performed before setting the endpoint enable bit in the
endpoint control register.
Once the endpoint is enabled, these fields are read-only as the OTG FS core updates them
with the current transfer status.
The following transfer parameters can be programmed:
•
Transfer size in bytes
•
Number of packets constituting the overall transfer size.
Endpoint status/interrupt
The device endpoint-x interrupt registers (DIEPINTx/DOPEPINTx) indicate the status of an
endpoint with respect to USB- and AHB-related events. The application must read these
registers when the OUT endpoint interrupt bit or the IN endpoint interrupt bit in the core
interrupt register (OEPINT bit in OTG_HS_GINTSTS or IEPINT bit in OTG_HS_GINTSTS,
respectively) is set. Before the application can read these registers, it must first read the
device all endpoints interrupt register (OTG_HS_DAINT) to get the exact endpoint number
for the device endpoint-x interrupt register. The application must clear the appropriate bit in
this register to clear the corresponding bits in the DAINT and GINTSTS registers.
1106/1381 RM0033 Rev 9
RM0033