ST STM32F207 Series Reference Manual page 1024

USB on-the-go full-speed (OTG_FS)
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 STSPHSRXM: Status phase received for control write mask
Bit 4 OTEPDM: OUT token received when endpoint disabled mask
Bit 3 STUPM: SETUP phase done mask
Bit 2 Reserved, must be kept at reset value.
Bit 1 EPDM: Endpoint disabled interrupt mask
Bit 0 XFRCM: Transfer completed interrupt mask
OTG_FS device all endpoints interrupt register (OTG_FS_DAINT)
Address offset: 0x818
Reset value: 0x0000 0000
When a significant event occurs on an endpoint, a OTG_FS_DAINT register interrupts the
application using the Device OUT endpoints interrupt bit or Device IN endpoints interrupt bit
of the OTG_FS_GINTSTS register (OEPINT or IEPINT in OTG_FS_GINTSTS,
respectively). There is one interrupt bit per endpoint, up to a maximum of 16 bits for OUT
endpoints and 16 bits for IN endpoints. For a bidirectional endpoint, the corresponding IN
and OUT interrupt bits are used. Bits in this register are set and cleared when the
application sets and clears bits in the corresponding Device Endpoint-x interrupt register
(OTG_FS_DIEPINTx/OTG_FS_DOEPINTx).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
r r r r r r r
Bits 31:16 OEPINT: OUT endpoint interrupt bits
Bits 15:0 IEPINT: IN endpoint interrupt bits
1024/1381
0: Masked interrupt
1: Unmasked interrupt
Applies to control OUT endpoints only.
0: Masked interrupt
1: Unmasked interrupt
Applies to control endpoints only.
0: Masked interrupt
1: Unmasked interrupt
0: Masked interrupt
1: Unmasked interrupt
0: Masked interrupt
1: Unmasked interrupt
OEPINT
r r r r r r
One bit per OUT endpoint:
Bit 16 for OUT endpoint 0, bit 19 for OUT endpoint 3.
One bit per IN endpoint:
Bit 0 for IN endpoint 0, bit 3 for endpoint 3.
r r r r r r r
RM0033 Rev 9
9 8 7 6 5
IEPINT
r r r r r r r
RM0033
4 3 2 1 0
r r r r r