ST STM32F207 Series Reference Manual page 1203

Advanced arm-based 32-bit mcus
Hide thumbs Also See for STM32F207 Series:
Table of Contents

Advertisement

RM0033
Table 168. OTG_HS register map and reset values (continued)
Offset
Register
OTG_HS_DO
EPINT6
0xBC8
Reset value
OTG_HS_DO
EPINT7
0xBE8
Reset value
OTG_HS_DIE
PTSIZ0
0x910
Reset value
OTG_HS_DIE
PTSIZ1
0x930
Reset value
OTG_HS_DIE
PDMA1
0x934
Reset value
OTG_HS_DIE
PDMAB1
0x93C
Reset value
0
OTG_HS_DIE
PTSIZ2
0x950
Reset value
OTG_HS_DIE
PDMA2
0x954
Reset value
0
OTG_HS_DIE
PDMAB2
0x95C
Reset value
0
OTG_HS_DIE
PTSIZ3
0x970
Reset value
OTG_HS_DIE
PDMA3
0x974
Reset value
0
OTG_HS_DIE
PDMAB3
0x97C
Reset value
0
OTG_HS_DO
EPTSIZ0
0xB10
Reset value
OTG_HS_DO
EPTSIZ1
0xB30
Reset value
OTG_HS_DO
EPDMA1
0xB34
Reset value
0
Reserved
Reserved
Reserved
MCN
PKTCNT
T
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MCN
PKTCNT
T
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MCN
PKTCNT
T
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
STU
PCN
Reserved
T
0
0
PKTCNT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
USB on-the-go high-speed (OTG_HS)
0
0
PKT
CNT
0
0
0
0
0
0
0
0
0
0
0
DMAADDR
0
0
0
0
0
0
0
0
0
DMABADDR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMAADDR
0
0
0
0
0
0
0
0
0
DMABADDR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMAADDR
0
0
0
0
0
0
0
0
0
DMABADDR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMAADDR
0
0
0
0
0
0
0
0
0
RM0033 Rev 9
0
0
0
0
0
0
0
0
Reserved
0
XFRSIZ
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
XFRSIZ
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
XFRSIZ
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reserved
0
XFRSIZ
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
XFRSIZ
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
XFRSIZ
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1203/1381
1260

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the STM32F207 Series and is the answer not in the manual?

Questions and answers

Table of Contents