ST STM32F207 Series Reference Manual page 1357

RM0033
Date
15-Apr-2011
Table 224. Document revision history (continued)
Version
CRYPTO:
Updated Section 19.1: CRYP
Modified Figure 195: Block
Updated Section 19.3.1: DES/TDES cryptographic
Section 19.3.2: AES cryptographic
HASH:
In Section 21.4.5: HASH interrupt enable register
renamed HASH_IMR into interrupt enable register, and bits DCIM
and DINIM into DCIE and DINIE, respectively.
Updated INIT bit description in
(HASH_CR).
RTC:
Added RTC_50Hz clock input for synchronous prescaler in
Figure 215: RTC block
Renamed digital calibration into coarse calibration.
Updated ALARMOUTTYPE definition.
Digital calibration renamed coarse calibration.
3
RNG:
(continued)
Renamed IM bit of RNG_CR register into IE.
I2C:
Updated BERR bit description in
(I2C_SR1).
Updated Note in
(I2C_CCR).
Updated requests in master receiver mode in
requests.
Added note 3 below
slave transmitter on page
Transfer sequence diagram for slave receiver on page
Section : Closing slave
description in
Modified Section 23.6.7: I
USART:
Updated Figure 231: Mute mode using address mark detection
Address =1.
Renamed ONEBITE to ONEBIT in USART_CR3 register.
RM0033 Rev 9
Changes
introduction.
diagram.
core, and
Section 21.4.1: HASH control register
diagram.
Section 23.6.6: I
2
Section 23.6.8: I C Clock control register
Figure 218: Transfer sequence diagram for
603. Added note below
communication. Modified STOPF, ADDR, bit
2
Section 23.6.6: I C Status register 1
2
C Status register 2
Revision history
core,
Table 74: Data types.
(HASH_IMR),
2
C Status register 1
Section 23.3.7: DMA
Figure 219:
604. Modified
(I2C_SR1).
(I2C_SR2).
for
1357/1381
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