ST STM32F207 Series Reference Manual page 1366

Revision history
Date
05-Nov-2012
16-Sep-2013
1366/1381
Table 224. Document revision history (continued)
Version
Debug:
Updated IO states after reset in
pull-down on JTAG
device ID code.
5
(continued)
Electronic signature:
Updated Section 33: Device electronic signature
as Section 33.2: Flash
PWR:
Updated Section 4.2.2: Brownout reset
Replaced "The backup domain includes 4 Kbytes of backup SRAM
accessible only from the CPU" with "The backup domain includes 4
Kbytes of backup SRAM" in
Updated Table 10: Stop
Updated description of "Bit 0 WUF: Wakeup flag" in PWR_CSR
register.
RCC
Modified description of PLLN bits in
configuration register
GPIO:
Removed frequency value in description of OSPEEDR bits.
Interrupts:
Updated Section 8.1.1: NVIC
6
DAC:
Updated Section 10.9.3: Interleaved
trigger mode, and
alternate trigger mode
RTC:
Removed "or when the Flash readout protection is disabled" in
Section 22.6.14: RTC backup registers
Replaced all occurrences of "power-on reset" with "backup domain
reset".
Replaced "System reset: 0x0000 0000 when BYPSHAD = 0. Not
affected when BYPSHAD = 1." with "System reset: 0x0000 0000
before the RSF flag is set, then the correct value is available in
Section 22.6.1: RTC time register
Replaced "System reset: 0x0000 2101 when BYPSHAD = 0. Not
affected when BYPSHAD = 1." with "System reset: 0x0000 2101
before the RSF flag is set, then the correct value is available in
Section 22.6.2: RTC date register
Added under
RM0033 Rev 9
Changes
Section 32.4.3: Internal pull-up and
pins.Updated REV_ID in
size.
Backup SRAM.
mode.
Section 5.3.2: RCC PLL
(RCC_PLLCFGR).
features.
mode,
Section 10.9.6: Combined regular simultaneous +
to describe case of interrupted conversion.
(RTC_TR).
(RTC_DR).
Table 80: RTC register map and reset
RM0033
Section 32.6.1: MCU
introduction as well
(BOR).
Section 10.9.4: Alternate
(RTC_BKPxR).
values.