ST STM32F207 Series Reference Manual page 1237

RM0033
3. The application must read the 2 words of the SETUP packet from the receive FIFO.
4. The application must read and discard the Setup stage done word from the receive
FIFO.
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Internal data flow
5. When a SETUP packet is received, the core writes the received data to the receive
FIFO, without checking for available space in the receive FIFO and irrespective of the
endpoint's NAK and STALL bit settings.
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6. For every SETUP packet received on the USB, 3 words of data are written to the
receive FIFO, and the STUPCNT field is decremented by 1.
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7. When the Setup stage changes to a Data IN/OUT stage, the core writes an entry
(Setup stage done word) to the receive FIFO, indicating the completion of the Setup
stage.
8. On the AHB side, SETUP packets are emptied by the application.
9. When the application pops the Setup stage done word from the receive FIFO, the core
interrupts the application with an STUP interrupt (OTG_HS_DOEPINTx), indicating it
can process the received SETUP packet.
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Application programming sequence
1. Program the OTG_HS_DOEPTSIZx register.
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2. Wait for the RXFLVL interrupt (OTG_HS_GINTSTS) and empty the data packets from
the receive FIFO.
3. Assertion of the STUP interrupt (OTG_HS_DOEPINTx) marks a successful completion
of the SETUP Data Transfer.
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The core internally sets the IN NAK and OUT NAK bits for the control IN/OUT
endpoints on which the SETUP packet was received.
The first word contains control information used internally by the core
The second word contains the first 4 bytes of the SETUP command
The third word contains the last 4 bytes of the SETUP command
The core clears the endpoint enable bit for control OUT endpoints.
STUPCNT = 3
On this interrupt, the application must read the OTG_HS_DOEPTSIZx register to
determine the number of SETUP packets received and process the last received
SETUP packet.
USB on-the-go high-speed (OTG_HS)
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