ST STM32F207 Series Reference Manual page 1170

USB on-the-go high-speed (OTG_HS)
OTG_HS Device threshold control register (OTG_HS_DTHRCTL)
Address offset: 0x0830
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Reserved
rw rw rw rw rw rw rw rw rw rw rw
Bits 31:28 Reserved, must be kept at reset value.
Bit 27 ARPEN: Arbiter parking enable
Bit 26
Bits 25: 17 RXTHRLEN: Receive threshold length
Bit 16 RXTHREN: Receive threshold enable
Bits 15: 11
Bits 10:2 TXTHRLEN: Transmit threshold length
Bit 1 ISOTHREN: ISO IN endpoint threshold enable
Bit 0 NONISOTHREN: Nonisochronous IN endpoints threshold enable
1170/1381
RXTHRLEN
This bit controls internal DMA arbiter parking for IN endpoints. When thresholding is enabled
and this bit is set to one, then the arbiter parks on the IN endpoint for which there is a token
received on the USB. This is done to avoid getting into underrun conditions. By default
parking is enabled.
Reserved, must be kept at reset value.
This field specifies the receive thresholding size in words. This field also specifies the
amount of data received on the USB before the core can start transmitting on the AHB. The
threshold length has to be at least eight words. The recommended value for RXTHRLEN is
to be the same as the programmed AHB burst length (HBSTLEN bit in
OTG_HS_GAHBCFG).
When this bit is set, the core enables thresholding in the receive direction.
Reserved, must be kept at reset value.
This field specifies the transmit thresholding size in words. This field specifies the amount of
data in bytes to be in the corresponding endpoint transmit FIFO, before the core can start
transmitting on the USB. The threshold length has to be at least eight words. This field
controls both isochronous and nonisochronous IN endpoint thresholds. The recommended
value for TXTHRLEN is to be the same as the programmed AHB burst length (HBSTLEN bit
in OTG_HS_GAHBCFG).
When this bit is set, the core enables thresholding for isochronous IN endpoints.
When this bit is set, the core enables thresholding for nonisochronous IN endpoints.
Reserved
RM0033 Rev 9
9 8 7 6 5 4
TXTHRLEN
rw rw rw rw rw rw rw rw rw rw rw
RM0033
3 2 1 0