ST STM32F207 Series Reference Manual page 1362

Revision history
Date
13-Dec-2011
1362/1381
Table 224. Document revision history (continued)
Version
FSMC:
Updated Section 31.3.1: Supported memories and transactions
Section 31.3: AHB
Changed Clock divide ration minimum value in
Programmable NOR/PSRAM access
Added register access in
registers and
Updated Table 172: NOR Flash/PSRAM supported memories and
transactions
Updated Table 191: FSMC_BTRx bit
FSMC_BTRx bit
4
Added Note 1 below
(continued)
below Figure 401: ModeA read
DEBUG:
Section 32.16.4: Debug MCU APB1 freeze register
(DBGMCU_APB1_FZ): added DBG_CAN2_STOP description for bit
26, and changed bit 24 to reserved. Updated bit 10 from reserved to
DBG_RTC_STOP in
Electronic signature:
Added Section 33.2: Flash size
register (96
RM0033 Rev 9
Changes
interface. Updated
Section 31.5.6: NOR/PSRAM control
Section 31.6.8: NAND Flash/PC Card control registers
for SRAM and ROM in asynchronous mode.
fields.
Figure 399: Mode1 read
accesses.
Table 223: DBG register map and reset
in Section 33.1: Unique device ID
bits).
RM0033
Section 27.4.2: Normal
Table 173:
parameters.
fields, and Table 194:
accesses, and Note 1
values.
and
mode.