ST STM32F207 Series Reference Manual page 1016

USB on-the-go full-speed (OTG_FS)
Bit 15 EPDIR: Endpoint direction
Bits 14:11 EPNUM: Endpoint number
Bits 10:0 MPSIZ: Maximum packet size
OTG_FS Host channel-x interrupt register (OTG_FS_HCINTx) (x = 0..7, where
x = Channel_number)
Address offset: 0x508 + 0x20 * x
Reset value: 0x0000 0000
This register indicates the status of a channel with respect to USB- and AHB-related events.
It is shown in
interrupt bit in the Core interrupt register (HCINT bit in OTG_FS_GINTSTS) is set. Before
the application can read this register, it must first read the host all channels interrupt
(OTG_FS_HAINT) register to get the exact channel number for the host channel-x interrupt
register. The application must clear the appropriate bit in this register to clear the
corresponding bits in the OTG_FS_HAINT and OTG_FS_GINTSTS registers.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits 31:11 Reserved, must be kept at reset value.
Bit 10 DTERR: Data toggle error
Bit 9 FRMOR: Frame overrun
Bit 8 BBERR: Babble error
Bit 7 TXERR: Transaction error
Bit 6 Reserved, must be kept at reset value.
Bit 5 ACK: ACK response received/transmitted interrupt
Bit 4 NAK: NAK response received interrupt
Bit 3 STALL: STALL response received interrupt
1016/1381
Indicates whether the transaction is IN or OUT.
0: OUT
1: IN
Indicates the endpoint number on the device serving as the data source or sink.
Indicates the maximum packet size of the associated endpoint.
Figure 357. The application must read this register when the host channels
Reserved
Indicates one of the following errors occurred on the USB.
CRC check failure
Timeout
Bit stuff error
False EOP
RM0033 Rev 9
9 8 7 6 5 4
rc_ rc_ rc_ rc_ rc_ rc_
w1 w1 w1 w1 w1 w1
RM0033
3 2 1 0
rc_ rc_ rc_
w1 w1 w1