Renesas H8 Series Hardware Manual page 10

Item
1.1 Overview
Table 1.1 Features
1.2 Internal Block
Diagram
Figure 1.1(1) Block
Diagram (H8/38024
Group, H8/38024R
Group, and
H8/38024S Group)
Figure 1.1(2) Block
Diagram (H8/38124
Group)
1.3.1 Pin
Arrangement
Figure 1.2(1) Pin
Arrangement
(FP-80A, TFP-80C:
Top View, H8/38024
Group, H8/38024R
Group, H8/38024S
Group)
Figure 1.3 Pin
Arrangement
(FP-80B: Top View,
H8/38024 Group,
H8/38024R Group)
Rev. 7.00 Mar 10, 2005 page x of xlii
Page Revision (See Manual for Details)
3, 6 Table amended
Item
Clock pulse
generators
Item
Product lineup
7 Figure amended
Asynchronous
counter
(16 bits)
8 Figure amended
Asynchronous
counter
(16 bits)
9 Description amended
The H8/38024 Group, H8/38024R Group, H8/38024S Group,
and H8/38124 Group pin arrangements are shown in figures
1.2, 1.3, and 1.4.
Figure title amended
11 Title amended
Specification
Two on-chip clock pulse generators
•
System clock pulse generator:
1.0 to 16 MHz: H8/38024 Group
1.0 to 10 MHz: HD64F38024, HD64F38024R, and H8/38024S Group
2.0 to 20 MHz: H8/38124 Group
•
Subclock pulse generator:
32.768 kHz, 38.4 kHz* (* does not apply to H8/38124 Group)
H8/38124 Group equipped with on-chip oscillator
Specification
Product Code
Mask ROM Version ZTAT Version F-ZTAT Version
HD64338122 — HD64F38122
IRQAEC
PA /COM
3 4
PA /COM
2 3
PA /COM
1 2
PA /COM
0 1
IRQAEC
PA
PA
PA
PA
Package
FP-80A
TFP-80C
/COM
3 4
/COM
2 3
/COM
1 2
/COM
0 1
ROM/RAM Size
(Byte)
16K/1K