Renesas H8 Series Hardware Manual page 391

Table 10.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2)
5 MHz
Bit Rate
(bit/s) n N
110 3 21
150 3 15
200 3 11
250 3 9
300 3 7
600 3 3
1200 3 1
2400 3 0
4800 2 1
9600 2 0
19200 0 7
31250 0 4
38400 0 3
Notes: No indication: Setting not possible.
—: Setting possible, but errors may result.
1. The value set in BRR is given by the following equation:
N =
(32 • 2
where B: Bit rate (bit/s)
N: Baud rate generator BRR setting (0 ≤ N ≤ 255)
φ: System clock frequency
n: Baud rate generator input clock number (n = 0, 2, or 3)
2. The error in table 10.3 is the value obtained from the following equation, rounded to two
decimal places.
Error (%) =
φ φ φ φ
8 MHz
Error Error
(%) n N (%)
0.88 3 35 –1.36 3
1.73 3 25 0.16
1.73 3 19 –2.34 3
–2.34 3 15 –2.34 3
1.73 3 12 0.16
1.73 2 25 0.16
1.73 2 12 0.16
1.73 0 103 0.16
1.73 0 51 0.16
173 0 25 0.16
1.73 0 12 0.16
0 0 7 0
1.73 — — —
φ
– 1
2n
• B)
(The relation between n and the clock is shown in table 10.4.)
B (rate obtained from n, N, OSC) – R(bit rate in left-hand column in table 10.3.)
R (bit rate in left-hand column in table 10.3.)
Section 10 Serial Communication Interface
10 MHz
Error
n N (%)
43 0.88
3 32 –1.36
23 1.73
19 –2.34
3 15 1.73
3 7 1.73
3 3 1.73
3 1 1.73
3 0 1.73
2 1 1.73
2 0 1.73
0 9 0
0 7 1.73
Rev. 7.00 Mar 10, 2005 page 349 of 652
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