Renesas H8 Series Hardware Manual page 120

Section 3 Exception Handling
Table 3.2 Interrupt Sources and Their Priorities
Interrupt Source Interrupt
Reset
R E S
Watchdog timer
IRQ
I R Q
0
Low-voltage detect interrupt *
LVDI *
IRQ
I R Q
1
IRQAEC IRQAEC
IRQ
I R Q
3
IRQ
I R Q
4
WKP
W K P
0
WKP
W K P
1
WKP
W K P
2
WKP
W K P
3
WKP
W K P
4
WKP
W K P
5
WKP
W K P
6
WKP
W K P
7
Timer A Timer A overflow
Asynchronous Asynchronous event
event counter counter overflow
Timer C Timer C overflow or underflow 13
Timer FL Timer FL compare match
Timer FL overflow
Timer FH Timer FH compare match
Timer FH overflow
Timer G Timer G input capture
Timer G overflow
SCI3 SCI3 transmit end
SCI3 transmit data empty
SCI3 receive data full
SCI3 overrun error
SCI3 framing error
SCI3 parity error
A/D A/D conversion end
(SLEEP instruction Direct transfer
executed)
Notes: Vector addresses H'0002 to H'0007, H'0014 to H'0015, and H'0022 to H'0023 are reserved
and cannot be used.
* The low-voltage detect interrupt triggered by the LVDI is only implemented on the
H8/38124 Group.
Rev. 7.00 Mar 10, 2005 page 78 of 652
REJ09B0042-0700
0
1
3
4
0
1
2
3
4
5
6
7
Vector Number Vector Address
0 H'0000 to H'0001
4 H'0008 to H'0009
5 H'000A to H'000B
6 H'000C to H'000D
7 H'000E to H'000F
8 H'0010 to H'0011
9 H'0012 to H'0013
11 H'0016 to H'0017
12 H'0018 to H'0019
H'001A to H'001B
14 H'001C to H'001D
15 H'001E to H'001F
16 H'0020 to H'0021
18 H'0024 to H'0025
19 H'0026 to H'0027
20 H'0028 to H'0029
Priority
High
Low