Renesas H8 Series Hardware Manual page 167

Bit 4—Noise Elimination Sampling Frequency Select (NESEL)
This bit selects the frequency at which the watch clock signal (φ
pulse generator is sampled, in relation to the oscillator clock (φ
pulse generator. When φ
Bit 4
NESEL Description
Sampling rate is φ
0
Sampling rate is φ
1
Bit 3—Direct Transfer on Flag (DTON)
This bit designates whether or not to make direct transitions among active (high-speed), active
(medium-speed) and subactive mode when a SLEEP instruction is executed. The mode to which
the transition is made after the SLEEP instruction is executed depends on a combination of other
control bits.
Bit 3
DTON Description
•
0
When a SLEEP instruction is executed in active mode,
a transition is made to standby mode, watch mode, or sleep mode
•
When a SLEEP instruction is executed in subactive mode, a transition is made to
watch mode or subsleep mode
•
1
When a SLEEP instruction is executed in active (high-speed) mode, a direct
transition is made to active (medium-speed) mode if SSBY = 0, MSON = 1, and
LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1
•
When a SLEEP instruction is executed in active (medium-speed) mode, a direct
transition is made to active (high-speed) mode if SSBY = 0, MSON = 0, and
LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1
•
When a SLEEP instruction is executed in subactive mode, a direct transition is
made to active (high-speed) mode if SSBY = 1, TMA3 = 1, LSON = 0, and MSON
= 0, or to active (medium-speed) mode if SSBY = 1, TMA3 = 1, LSON = 0, and
MSON = 1
Bit 2—Medium Speed on Flag (MSON)
After standby, watch, or sleep mode is cleared, this bit selects active (high-speed) or active
(medium-speed) mode.
= 2 to 20 MHz, clear NESEL to 0.
OSC
/16
OSC
/4
OSC
Section 5 Power-Down Modes
) generated by the subclock
W
) generated by the system clock
OSC
Rev. 7.00 Mar 10, 2005 page 125 of 652
(initial value)
(initial value)
REJ09B0042-0700