Renesas H8 Series Hardware Manual page 652

Appendix B Internal I/O Registers
IRR1—Interrupt Request Register 1
Bit 7
IRRTA
Initial value 0
R/(W) *
Read/Write
Timer A Interrupt Request Flag
0 Clearing condition:
1 Setting condition:
Note: * Bits 7 and 4 to 0 can only be written with 0, for flag clearing.
Rev. 7.00 Mar 10, 2005 page 610 of 652
REJ09B0042-0700
6 5
 

1

W
IRQAEC Interrupt Request Flag
0 Clearing condition:
When IRREC2 = 1, it is cleared by writing 0
1 Setting condition:
When pin IRQAEC is designated for interrupt
input and the designated signal edge is input
IRQ4 and IRQ3 Interrupt Request Flags
0 Clearing condition:
When IRRIm = 1, it is cleared by writting 0
1 Setting condition:
When pin IRQm is designated for interrupt
input and the designated signal edge is input
When IRRTA = 1, it is cleared by writing 0
When the timer A counter value overflows (from H'FF to H'00)
H'F6
4 3
IRRI4 IRRI3 IRREC2
0 0
R/(W) * R/(W) * R/(W) *
IRQ1 and IRQ0 Interrupt Request Flags
0 Clearing condition:
When IRRIn = 1, it is cleared by writing 0
1 Setting condition:
When pin IRQn is designated for interrupt
input and the designated signal edge is input
(m = 4 or 3)
System Control
2 1 0
IRRI1 IRRI0
0 0 0
R/(W) * R/(W) *
(n = 1 or 0)