Renesas H8 Series Hardware Manual page 127

Bit 7—Timer A Interrupt Request Flag (IRRTA)
Bit 7
IRRTA Description
0
Clearing conditions:
When IRRTA = 1, it is cleared by writing 0
1 Setting conditions:
When the timer A counter value overflows
Bit 6—Reserved
Bit 6 is reserved; it can only be written with 0.
Bit 5—Reserved
Bit 5 is reserved; it is always read as 1 and cannot be modified.
Bits 4 and 3—IRQ and IRQ
4
Bit n
IRRIn Description
0 Clearing conditions:
When IRRIn = 1, it is cleared by writing 0
1
Setting conditions:
When pin
input
Bit 2—IRQAEC Interrupt Request Flag (IRREC2)
Bit 2
IRREC2 Description
0 Clearing conditions:
When IRREC2 = 1, it is cleared by writing 0
1 Setting conditions:
When pin IRQAEC is designated for interrupt input and the designated signal edge is
input
Interrupt Request Flags (IRRI4 and IRRI3)
3
is designated for interrupt input and the designated signal edge is
I R Q n
Section 3 Exception Handling
Rev. 7.00 Mar 10, 2005 page 85 of 652
(initial value)
(initial value)
(n = 4 or 3)
(initial value)
REJ09B0042-0700