Timer Operation - Renesas H8 Series Hardware Manual

8-bit single-chip microcomputer

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Timer Operation

The watchdog timer has an 8-bit counter (TCW) that is incremented by clock input. The input

clock is selected by the WDCKS in port mode register 2 (PMR2): on the H8/38024, H8/38024S,

and H8/38024R Group, φ/8192 is selected when WDCKS is cleared to 0, and φw/32 when set to 1.

On the H8/38124 Group, if WDCKS is cleared to 0 the clock selection is specified by the setting

of timer mode register W (TMW), and if WDCKS is set to 1 the φw/32 clock source is selected.

When TCSRWE = 1 in TCSRW, if 0 is written in B2WI and 1 is simultaneously written in

WDON, TCW starts counting up. (Write access to TCSRW is required twice to turn on the

watchdog timer. However, on the H8/38124 Group WDON is set to 1 after a reset is cancelled,

TCW starts to be incremented even without gaining write access to TCSRW.) When the TCW

count value reaches H'FF, the next clock input causes the watchdog timer to overflow, and an

internal reset signal is generated one base clock (φ or φ

output for 512 clock cycles of the φ

count up from the written value. The overflow period can be set in the range from 1 to 256 input

clocks, depending on the value written in TCW.

Figure 9.18 shows an example of watchdog timer operations.

Internal reset

Figure 9.18 Typical Watchdog Timer Operations (Example)

clock. It is possible to write to TCW, causing TCW to

Example: φ = 2 MHz and the desired overflow period is 30 ms.

The value set in TCW should therefore be 256 − 8 = 248 (H'F8).

H'F8 is written

H'F8 is written in TCW

) cycle later. The internal reset signal is

TCW overflow

Rev. 7.00 Mar 10, 2005 page 309 of 652

Section 9 Timers

clock cycles

REJ09B0042-0700